TIMING ANALYSIS OF CMOS INVERTER

Abstract

Propagation delay is one of the most critical performance parameter in CMOS digital circuits. Using transistor level simulators with continuous time modeling of the devices like SPICE can be very expensive in terms of storage and computation time. The main goal of this work is the analytical evaluation of the propagation delay in a CMOS inverter. To achieve these goel efforts devoted for the extraction of accurate, analytical expression for the timing models of basic circuits has been studied. Three such analytical models of calculating delay, considering the effect of gate to drain coupling capacitance and short circuit power dissipation have been applied on simple and accurate a power MOS model current voltage equations. The accuracy of the models is measured by comparison with SPICE simulation. It is important to note that all these analytical methods define the propagation delay as the time interval at which input and output voltage crosses the half supply voltage finally these improved approaches of calculating delay have been applied on a circuit drawn in L-Edit and a comparison with layout simulation has been made.