MODELING A DIGITAL DATA PROCESSING SYSTEM USING HARDWARE DESCRIPTION LANGUAGE

Abstract

Model of space switch, A digital data processing system using Hardware Description Language (HDL) has been developed. The detailed design of a complex digital system at the gate level and flip-flop level has become very tedious and time consuming. The presented work describes the implementation of space switch (A time division time multiplexed switching) in FPGA chip which overcome to the above problem. The space switch contains a structural model at top level include blocks at lower level, the block level models contains behavioral model. The block level model, memory block and switching block are modeled using behavior style (sequential assignment statements). The work is focused on designed methodologies based on tools and techniques to capture the design to simulate it at several levels of abstraction and to implement it through synthesis. The VHDL model of space switch includes both behavioral and structural level. It is analyzed to remove all possible syntax errors using VHDL analyzer. The VHDL system simulator (Active HDL) then simulates debug VHDL codes to check for the functionality of the chip as per the specifications. To synthesize the chip, design compiler is used which converts VHDL description to block level (inbuilt blocks) or gate level implementation into a given target technology. Synthesis optimization tools are used to convert the chip design into smaller area and faster speed. The synthesizer converts the VHDL code into a bitmap binary file which is input to implement tools, lastly the synthesized design is verified and various synthesis post and pre synthesis, simulation, Place And route reports are analyzed- to evaluate and verify the performance of the designed chip.