Please use this identifier to cite or link to this item:
|Title:||INFLUENCE OF HIGH FIELDS ON STANDBY POWER DISSIPATION OF CMOS GATES|
|Keywords:||PHYSICS;POWER DISSIPATION;CMOS GATES;HIGH FIELDS|
|Abstract:||The main contribution to standby power dissipation comes from the subthreshold leakage current. Hence, it is mandatory to develop a holistic model which accounts for all important physical phenomena taking place in the subthreshold regime. These include drift-diffusion, thermionic emission, short channel effects and high field effects. The subthreshold model has been specifically modified to include the high field effect in subthreshold region i.e., impact ionization which ultimately leads to avalanche breakdown. The standby power dissipation of a CMOS circuit is calculated using the concept of dominant leakage states, input state probabilities and the model mentioned above. Finally, the effect of multiplication on the standby power dissipation of the circuit is studied with respect to the applied inputs.|
|Research Supervisor/ Guide:||Sarkar, S.|
|Appears in Collections:||MASTERS' THESES (Physics)|
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.