Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/382
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dc.contributor.authorPradhan, Kailash Charan-
dc.date.accessioned2014-09-14T13:04:33Z-
dc.date.available2014-09-14T13:04:33Z-
dc.date.issued1986-
dc.identifierPh.Den_US
dc.identifier.urihttp://hdl.handle.net/123456789/382-
dc.guideSharma, Jaydev-
dc.description.abstractWith the advancement in integrated circuit technology, the size and complexity of the electronic circuits have increased at an astonishing rate during the last decade. Therefore to reduce the time and cost of the design, it is important and necessary to perform thorough verification of the design prior to fabrication. The design process may be classified into three separate, though interacting phases i.e., a feasibility study, a preliminary design phase, and a detailed design phase. In the first phase of the design process, on the basis of the circuit objectives, acceptable design solutions are determined, consi dering the economy and physical realizability aspects. Thus in the feasibility, study, number of feasible solutions are proposed by the designer, exercising ail his experience and < creativity. The first step in the preliminary design is to choose for further study, the most promising topology of the circuit from the feasible solutions. Having done this, the designer has to determine values for circuit components such that the best possible circuit performance resxilts, without changing the topology of the circuit. The detailed design phase includes preparation of detailed component specifications and assembly drawings, testing of proto-types, etc. Some aspects of circuit design process such as circuit analysis (i.e., d. c, a. c, transient) and the optimal design of circuit parameters without changing topology, considering component variations and environmental effects have been ii investigated in this thesis. In circuit performance determination and circuit opti mization, most algorithms require the solution of a large set of non-linear algebraic and differential equations. There are many methods available for electronic circuit analysis. Most of the existing circuit analysis algorithms employ Newton's method based scheme For solving non-linear algebraic equations as Newton's method and its modifications are efficient end reliable. h% this thesis, an efficient and reliable modified Newton's method is developed for the analysis of large electronic circuits by exploiting the properties of semiconductor devices, The method developed doe« not require the hifgier order derivati ves. In existing methods the circuit equations are formed in terms of node voltages whereas Newton's corrections in the junction voltages of the bipolar devices when junction is forward biased, are modified logarithmically to improve the convergence. But the node voltages, with this correction in the junction voltages, are not modified properly, which may cause slow convergence due to more round off error and make the methods less reliable. In the presented method the node voltages, after the correction in junction voltages, are determined with the help of a selected spanning tree and node to datum path matrix to enhance the convergence rate and reliability. The algorithm developed exploits efficiently the sparsity of the nodal admittance matrix to reduce computational effort and memory requirement* A method for the solution of electronic circuits consisting iii of components having not hi -£ily non-linear characteristics such as MOSFET device, is also developed,, Newton's method and its modifications require the computation of first order derivative matrix of circuit equations at each iteration. In the proposed method, properties of MOSFET device have been exploited to avoid the need of computation of the Jacobian matrix and its LU factorization in each iteration. Thus the method is more efficient than the existing methods. The suggested method can also be used for the analysis of bipolar devices after minor modifications,, In a well designed circuit, the temperature rise of any of the circuit component due to power dissipation in it, should not exceed a certain limit to avoid the damage of component due to overheating and also to keep the deterioration of circuit performance within limits. An algorithm is developed to consider the effect of temperature rise due to self-heating on the performance of the circuit. In circuit optimization method, fixed circuit structure is :' optimized by adjusting seme designable parameters in order to achieve the desired circuit response. The required circuit response or design objectives are translated into a set of specific scalar functions or performance functions. The design problem can be stated so as to minimize a performance function subject to circuit equations and limits on problem variables. The method developed for optimal design of electronic circuit is based on reduced gradient and gradient projection technique because of its low storage requirement, efficiency iv and reliability. All problem variables are decomposed into two sets i.e., independent and dependent variables. Desienable parameters are taken as independent variables. Circuit variables (nodal voltages and branch voltages and currents) are taken as dependent variables. The decomposition of variables results in the reduction of size and complexity of the problem. Computation of sensitivity of the performance function with respect to various designable parameters are derived using adjoint network approach. The final step consists of cost based optimal design of electronic circuit. Cost and circuit response are both function of component tolerances. Larger tolerances in the circuit components will result in reduced cost of the net-work. On the other hand, the use of such components may deteriorate the circuit performance to violate the desired specification. Therefore, compromise is to be made between the cost and performance of the network. In the existing methods for cost based optimal design, largest tolerances of the circuit compo nents are determined, not to violate the extreme limits of circuit performance. In this thesis, an optimization problem has been formulated to minimize the objective function, consis ting the cost of components in terms of their tolerances, and a penalty term for violating the desired performance. Thus the factors governing both the cost and quality of the network are included in the same objective function. An algorithm is developed to optimize the proposed objective function.en_US
dc.language.isoenen_US
dc.subjectELECTRONIC CIRCUITSen_US
dc.subjectDESIGN AND ANALYSISen_US
dc.subjectCIRCUIT DESIGNen_US
dc.subjectCIRCUIT LAYOUTen_US
dc.titleDESIGN AND ANALYSIS OF LARGE ELECTRONIC CIRCUITSen_US
dc.typeDoctoral Thesisen_US
dc.accession.number179223en_US
Appears in Collections:DOCTORAL THESES (Electrical Engg)

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