Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/372
Title: DESIGN AND DEVELOPMENT OF RELIABILITY ANALYSER
Authors: Bansal, B. K.
Keywords: DESIGN AND DEVELOPMENT
RELIABILITY ANALYSER
DIGITAL PROGRAM
MICROPROCESSOR
Issue Date: 1982
Abstract: The graph theory can be applied for the evaluation of reliability of non-maintained systems operating with built in redundancy. The evaluation of terminal reliability or global reliability, for the most general case of non series parallel network requires the determination of either the minimal paths or the minimal cuts or the spanning trees. A number of algorithms and computer programmes are available in the literature, which are suitable for digital computers. The recent advances in electronics, particularly the introduction of microprocessors, has resulted in the development of dedicated desk top equipments, for functions which were performed by large computers. The new set of equipments have easy accessibility and can be easily incorporated in large scale systems for ON line control and monitoring applications. A similar exercise is also necessary in the field of graph theory because graph theory and associated concepts are used not only in Reliability engineering but in wide variety of other areas. Analyzer A Reliability has been designed, developed and tested which has the facilities to find the spanning tree?, the minimal paths and minimal cuts of a given graph, starting from its incidence matrix. A set of algorithm using a special tracing process, based on search techniquete-v-c been presented so that the design of the equipment is feasible with commercially available components. In the new approach the desired graph is traced starting from any one node of the graph. The tracing process is organised by assigning binary counters to each node of the graph. The state of a counter at any instant represents a particular set of branches which connect the particular node to the rest of the graph. The checks are provided at each step so that only the desired graphs are generated. . The above algorithm has been used to design a spanning tree generator using sequential circuits. However, the design becomes very complex even for very simple graphs. It was felt that a microprocessor based system with its programming feature could reduce the size and complexity of the hardware design. A software design of a spanning been tree generator has/carried out to establish that the hardware implementation of the algorithm is possible for reasonably large graphs. The special tracing process can also be used to find the minimal paths and minimal cuts. In the case of minimal paths the counters assigned to the nodes of the graph do not include the states with multiple selection. The tracing process begins at the starting node, and a minimal path is declared when the end node is joined. The minimal cuts are formed by applying the special tracing process on the set of minimal paths. Each path is assigned a path counter with as many states as the number of branches included in it. The tracing process begins on any path. Each branch intersects a set of paths. When all the paths have been intersected a cut is found. The minimal cutset is found by a continuous comparison of the cuts generated as above. The complete software design of a microprocessor based Reliability Analyser has been presented. A microprocessor based Reliability Analyser has been designed developed and tested. The software design is permanently stored in a PROM of 4K byte capacity. The equipment has a working memory of 2K bytes, which is sufficient for a graph of 100 branches. A part of the above memory capacity is also available to store the end results. The equipment includes a keyboard with Data keys to enter the incidence matrix and Function keys to verify the input data, to execute the programme, and to display the end results. The Reliability Analyser with its programming feature can also be used for a wide variety of linear programming problems such as the maximal flow problem, the postman problem, the sales manager problem; etc. The special tracing process discussed in the present thesis has been used to develop a new set of algorithms for the been solution of above problems. It has also/possible to use search technique to find minimal paths and minimal cuts of directed graphs. The development of Reliability Analyser is the beginning of the process of providing desk top equipments to the system designers. There is an immense scope to increase the capabilities of the Reliability Analyser which has been designed, developed and tested. Many more functions can be incorporated without making any change in its hardware design. Besides this, every year new microprocessors are being developed which are faster and have more powerful instruction sets. Hence it should be possible to implement algorithms with more complex arithmatic and logic operations. It is envisaged, that ultimately it will be possible to design small desk equipments with many more functions which are presently being handled by large computers.
URI: http://hdl.handle.net/123456789/372
Other Identifiers: Ph.D
Appears in Collections:DOCTORAL THESES (Electrical Engg)

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