Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/369
Title: WORST-CASE DESIGN OF CIRCUITS
Authors: Pillai, K. Ramachandran
Keywords: WORST-CASE
DESIGN OF CIRCUITS
PROGRAMMING TECHNIQUE
GEOMETRIC PROGRAMMING
Issue Date: 1981
Abstract: In every circuit design the final step consists of a tolerance analysis. In order to keep the cost of a network minimum, we should determine the largest tolerance that can be assigned to its component values. With the advancement in the computer-aided design the tolerance allocation problem has also assumed new dimensions. For a given range of possi ble values of tolerance, the possible values of the output of a network can be determined. If enough sets of component values and their tolerances are chosen, an accurate estimate of the range of output can be found out using a Monte-Carlo analysis. This is called the w0rst-Case tolerance analysis problem. But we should design the largest tolerance which each component can have, and still have the network satisfy its performance requirements within acceptable limits. This design problem is referred to as the worst-case design of tolerances. There are two different applications of worstcase design. The first one is used in the economical mass production of circuits where hundred percent manufacturing yield is not required. The second application is in the design of complicated electronic circuits which perform with precision but assumes hundred percent yield. The latter aspect of worst-case design has been used for assigning tolerances in circuits, in this dissertation. The optimal allocation of tolerances to obtain a minimum cost network that satisfies performance specifica tions within acceptable limits is designated as the tole rance assignment problem. An associated concept of tolerance assignment i8 the tuning of circuits. Complex miniaturized Integrated circuits cannot be manufactured without using a tuning procedure. The batch fabrication techniques of hybrid, thin-film and thick-film capacitors and resistors manufacture them with tolerances in the + 5 percent range. Sophisticated circuits such as high performance R.C.filter circuits may require tighter element tolerances to meet the required performance characteristics. Also the lossy capa citors and non-ideal characteristics of operational amplifiers tend to deviate the aexual characteristics of such circuits from its ideal or nominal ones. Thus tuning becomes a requir ed process to trim circuit elements to meet performance requirements. In this dissertation the twin aspects of optimal tolerance assignment and tuning of circuits associat ed with network design have been investigated. Cost and circuit response are both functions of compo nent tolerances. Larger, tolerances in circuit components will result in reducer1 cost of the network. On the other hand circuit performance achieved by such components may not meet the desired specifications. Therefore a trade-off is to be performed between the cost of the network and the variability in its performance. The tolerance allocation problems have been formulated so as to minimize the cost of the network subject to the constraints on the variance of the network performance specifications. An optimization problem has been formulated to minimize the cost function consisting of the tolerances. The constraints on the variance of the circuit frequency response have been consi dered in this problem. The variance in the circuit perfor mance has been expressed in terms of the sensitivities of the components. F0r known probability distribution, the performance variances have been developed in terms of the sensitivities and tolerances of the components. The sensi tivities of the network elements have been calculated using return difference method. The advantage of the method used for sensitivity calculation is that it lends itself to be easily computerized and is quiet efficient. In this work an attempt has been made to develop some efficient methods of tolerance assignments in circuits. Both the aspects of continuous and discrete tolerance assignment have been considered in detail. The optimization problem formulated for the tolerance assignment is constrained non-linear programming problem. For assigning continuous tolerance this constrained problem is converted into un constrained optimization problem using Lagrange multipliers. The solution to the Lagrangian is achieved by two different procedures. In the first method it is solved with the help of modified-Newton method. The optimality condition of the Lagrangian yields a set of (n + m) non-linear equations where n is the number of components and m represents the number of network constraints. These non-linear equations are linearised and the optimum solution is obtained using modified-Newton method. The solution procedure involves an inversion of a Jacobian which is achieved efficiently by the matrix partitioning technique to minimize computa tional efforts. This has been found advantageous especially for networks with uniform or evenly shaped frequency response characteristics, as in such cases the order of the matrix to be inverted becomes small. The method has been demonstra ted in the design of a passive band pass circuit. For assigning tolerances in large networks non linear programming techniques cannot be efficiently used as computational effort increases exponentially with increase in number of variables of the network. Therefore multi level techniques can be used, in such cases. The multilevel techniques involves the decomposition of a problem into a number of subproblems of much lesser dimensions. Thus in the second method, the use of Lagrange multipliers is made to decompose continuous tolerance allocation problem into subproblems by taking advantage of the separability of the variables. This results into n-subproblems for a problem of n-circuit elements. These subproblems are then solved by modi fied Newton method. The results of the subproblems ere then co-ordinated by modifying the Lagrange multipliers. This nested procedure of solving the subproblems and modifying the Lagrange multipliers is repeated until the optimum solution is obtained. This procedure has an advantage since the individual subproblems can be solved more easily than the original problem. This technique has the further advantage of requiring less computer time and reducing the problem complexity at the same time. An example of a band pass filter circuit design has been used to elucidate the technique. A geometric programming of tolerance assignment problem is also presented for a special type of objective function. The expressions for optimal component tolerance in the circuit are derived, For problems with one constraint the number of terms in the geometric programming formulation exceeds the number of variables by one. This gives a unique solution of the dual problem which can be solved easily by mere hand calculations, and hence the advantage of the technique. A method has also been suggested for solving problems with multiple constraints. A band pass filter circuit problem has been solved using this method. Although an appreciable material on continuous tolerancing is available in literature discrete tolerance allocation vi has not received much attention of the researchers. A serious endeavour along this direction has been made in this thesis. With this aim, a beta function type penalty is intro duced in the Lagrangian to convert continuous variables into discrete ones. The beta type penalty function sustains the decision variables of the Lagrangian discrete during the entire solution process. The use of the discretizing penalty extricate the variables from the restriction of being inte gers and hence the formulation involves less number of variables than other integer-programming formulation of tole rance allocation problem. The technique has been elucidated in the solution of discrete tolerance assignment in a passive and an active circuit. Yet, another efficient approach has been developed in this thesis to assign discretized tolerance of the components in a circuit. The tolerance problem is first converted into a zero-one programming problem which has a special structure. By exploiting the special structure, the problem is solved by a partial enumeration technique. This method also requires less computation time than earlier methods* The drawback of the method, however, lies in the fact that the number of variables in this type of formulation is larger than in other methods. The method has been illustrated by using it for the Vll tolerance allocation of both an active and a passive circuit. The existing methods to solve integer-programming formulation of discrete tolerance assignment problem are computer-dependent. There may be instances when a costly exact solution with the aid of computer is not more attrac tive than an easily found suboptimal solution. In the case of discrete tolerance assignment problem also, it may not be always necessary to find out the exact solution. There may be situations when improvements are to be effected in the breadboard design only. Or there may be instances of cir cuits which calls for excessive computer memory but requires a suboptimal solution only. In such cases, for solution of tolerance assignment problem heuristic methods have been proposed to assign discrete tolerances in circuits. In all the three methods the tolerance allocation have been obtained by hand calculations thereby dispensing with the use of the costly computer time and memory. Finally, the tuning problem of network has also been analysed. A high performance R.C. filter circuit has been considered for tuning. In the method proposed, the magnitude of resistors to be tuned are predetermined. The tuning problem has been formulated as a mathematical programming problem. The pre-assumed values of resistors form the problem variables. Vlll The mean square error between them and the designed values of resistors is minimized. The constraints for the optimization problem have been developed on the basis that the phase requirements of the ideal and actual circuits must be identi cal for the same frequency of operation. The advantage of the technique is its non-iterative procedure and the feasibility for preproduction tuning. It is thus superior to simulation type tuning which is usually implemented as a post-fabrication process and is time-consuming. In this way the objectives of this attempt to provide some efficient and practical algorithms for network design problems which involve tolerancing and tuning have been achieved.
URI: http://hdl.handle.net/123456789/369
Other Identifiers: Ph.D
Appears in Collections:DOCTORAL THESES (Electrical Engg)

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