PERFORMANCE OPTIMIZATION OF ELECTRONIC CIRCUITS

Abstract

Y/ith the development of integrated circuit technology, the size and complexity of circuits have grown tremendously. Due to higher speed, frequency and accuracy, and miniaturization of electronic components and circuits, there is considerable interaction between elements of the circuit. It is therefore, necessary to perform detailed study of the circuit design prior to fabrication. The circuit design process can bo described in a simple way as follows* The first step in the design process is to determine the initial structure of the circuit (i.e., to determine what its components and their functional relationships are) on the basis of circuit objectives and to test it to a rather loose specification to see whether it is worthwhile proceed ing in detail. In the case of large circuits, this will require some method of circuit analysis and computer simulation. Having satisfied a loose specification, the designer will then prepare the tighter and complete design specification for the circuit which should translate desired operating characteristics under all anticipated service conditions into circuit configuration and hardware require ments. Specification includes environmental performance, operational roquiroments under noraal and abnormal conditions, reliability requirements, dimensions and cost. The next stage of design is to optimize the fixed circuit structure to meet above specification. Now designer will transfer the design to mechanical layout suitable for production, with the electrical and physical constraints. Last step in the design process is to evaluate the reliability and availability of the circuit. If the designed circuit does not have desired reliability level, either the circuit is to be redesigned or alternative measures for reliability improvements have to be investigated and implemented. Certain aspects of circuit design process such as circuit analysis, the optimal choice of designablc parameters (i.e. optimization of fixed circuit structure), reliability analysis and the mechanical layout of circuit have been investigated in this dissertation. In circuit optimization, most of the algorithms evaluate the numerical values of the performance functions and its gradient with respect to the designablc parameters at several points during the optimization procedure. The evaluation of the scalar performance function and its gradient involve analysis of a large set of non-linear algebraic and diff erential equations. Many algorithms arc available in the literature to solve non-linear electronic circuit equations based on Newton's method. But the properties of semiconductor devices have not been fully exploited to improve the conver gence rate and reliability of the algorithms. In this study a very efficient and reliable algorithm for the analysis of non-linear electronic circuits is developed by exploiting the properties of semiconductor devices, which does not require the higher order drivatives of circuit equations. This algorithm is then applied for the transient and d.c. analysis of few electronic circuits and a comparison study is carried out with the available fast algorithm. For the analysis of large electronic circuits, it is extremely difficult to use the above-mentioned programmes due to large number of variables. Besides computation effort increases exponentially with the increase in number of variables. To overcome these difficulties, a decomposi tion method is developed. In this method a large circuit is decomposed into a number of sub-circuits and each subcircuit is solved independently. The original circuit is then analysed by coordinating the results so obtained from subcircuits iteratively. This method requires less computer memory and is very efficient. It is applicable for the analysis of linear and non-linear circuits. In a circuit optimization program, fixed circuit structure is optimized by adjusting some designable parameters in order to achieve the desired circuit response. Two methods are presented for optimization of non-linear d.c. electronic circuits. First method uses generalized reduced gradient technique. In this method all problem variables are decomposed into two sets i.e. independent and dependent variables which reduces the complexity of the problem. Designable parameters are taken as independent variables. Branch currents, node -IVand branch voltages are taken as dependent variables. Computation of gradient of the performance function with respect to independent variables dOv_s not require adjoint network and its solution. In second method circuit is decomposed into smaller circuits, each with its own goal and constraints. The optimal solution for original circuit I is obtained by solving each subcircuit independently and coordinating the results so obtained iterativcly. The cost, performance, maintenance and reliability of a circuit depends en the placement of circuit components on the printed circuit board and routing. The new and more refined mathematical placement models based on the criteria related to the (a) length of etches, (b) inter connection density, (c) stray capacitance and (d) temperature rise of devices, are developed for mechanical layout of the circuit. An efficient iterative algorithm based on sensitivity analysis is presented to achieve optimal placement. Express ions are derived to reduce the computational efforts involved in sensitivity analysis. Now a days, reliability is an inherent attribute of a circuit just as is the circuit capacity or power rating. It is economical to consider circuit reliability at design stage rather than at a later stage. The circuit reliability analysis furnishes the designer an estimate of the theoretically achievable reliability and points out the ar-_a of high-failure rate concentration in the larg; and • -Vcomplex circuit:s. Later the areas of high-failure rate may be eliminated -by judicious usa of redundancy techniques, by reduncing circuit complexity or by using highly reliable components. A delta-star transformation approach has been developed to evaluate the reliability of the complex reliability block diagrams consisting of 2-state cr 3-state devices. Conditions are given under which the exact delta-star transfor mation is possible. An efficient method for computing the symbolic steady state availability of a k-out- of -n: G circuit with and without spares is developed. The model extends the usual k--out-of-n:G circuit by considering repair, installation, spares and off line failures. An algorithm is presented for generating all the states and transition matrix of 'Jc-.out-of-n:G circuit with spares' by computer. An algorithm is also developed to evaluate intrees of the state transition, diagram which are required to evaluate the expression for steady state availability. This method is also applicable, in general, to evaulate s.s. availability of a circuit whose state transition matrix or transition diagram is known. A simple procedure is also described to determine transition diagram of 'k-out-of-nsG circuit with spares' without calc ulating state transition matrix.