MITIGATION OF RADIATION EFFECTS IN MOS BASED DEVICES AND CIRCUITS

Abstract

Cosmic rays and alpha particles remain the dominant factors which degrade the performance of modern electronic systems. It has been widely reported that there are many critical applications that got affected by the radiations. Protection against the effects of radiation is very important for space, biomedical, computing and communication applications. In the past, radiation effects were limited to only hostile environments such as space. However, with the advances in the process technology, the charge stored at the circuit node decreases dramatically due to the shrinking transistor geometries and decreased supply voltages. Thus low energy particles at the ground level can also cause upsets. The importance of effectively dealing with routing infrastructure of the internet or data corruption issues in medical electronics cannot be understated. In bulk Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), radiation induced charges are mainly corrected by the funneling effect. However, in silicon on insulator (SOI) MOSFETs, the parasitic bipolar effect leads to single event upset (SEU). Lattice damage and ionization damage are the two fundamental physical damage mechanisms that take place in MOS devices exposed to radiations. Total-ionizing-dose (TID) and single-event-effects (SEE) are the two major categories of radiation effects on integrated circuits. One of the primary motivations behind development of SOI technology is its intrinsic hardness to radiation due to the presence of buried oxide. However, scaling has drastically reduced on-chip capacitances, leaving the logic on recent generation hardware vulnerable to radiation induced upset. With the devices being scaled down, there is an increase in the SEU not only in bulk but also in SOI devices. To resolve the scaling issues, the multiple gate technology is the most promising among the alternatives to conventional single gate (SG) technologies. However, TID as well as SEE in multiple gate devices have not been extensively studied yet, mostly because these devices are still at an early stage of development. Only recently, total-dose experiments on advanced multiple gate structures have been performed. For present day multiple-gate devices the orders of magnitudes of radiation effects have to be re-considered. This thesis primarily deals with the study of radiation effects; TID as well as SEE in MOS based devices and circuits. This thesis also introduces radiation environment, sources, radiation damage mechanism in semiconductor devices and their effects in integrated circuits. An extensive literature survey pertaining to the state of the art in the area of study is presented. Many important research papers are referred and cited which allow one to fully appreciate the usefulness of mitigation of radiation effects in present day devices and circuits. Various research gaps are identified based on extensive literature review. Modeling and simulation is an ongoing topic of research for many engineers and device physicists to accurately predict the behavior of fabricated devices. The purpose of modeling is to derive simple, fast and accurate analytical (mathematical equations) representations of the terminal electrical characteristics of devices. Simple analytical models of the MOS transistors are needed for computer-aided design of circuits containing thousands to millions transistors on a silicon chip. Compact models are needed to compute analytically the device characteristics, rapidly enough, for use in circuit simulators to design and optimize the performance of circuits containing thousands to millions of similar and dissimilar transistors. There are several studies that deal with the effect of irradiation on threshold voltage and device characteristics of MOSFETs. Analytical models for estimation of electrical characteristics of irradiated single gate MOS device have been widely reported. However, analytical models for irradiated multiple-gate devices such as FinFET have not yet been reported. The generation of traps in the BOX and the interface traps at the sidewall of the fin, influence the electrical characteristics of an irradiated FinFET device. This thesis deals with the development of analytical model for threshold voltage, mobility, drain current and leakage current in irradiated FinFET device. The effect of quantum mechanical confinement has also been included in the developed model. The models developed for irradiated FinFET device are validated against reported experimental data and TCAD simulation results. The results obtained on the basis of our model were found to be a close match with the reported results thus ensuring the accuracy of the model developed. This thesis also presents the TCAD simulation studies of effect of radiations on bulk structure, SOI, FinFET and 3D SRAM cell. Effective methods for the mitigation of radiation effects in MOS devices are indentified with TCAD simulation of different kind of devices. The concept of 'Linear Energy Transfer' (LET) and funneling mechanism in bulk structure has been presented. The only radical technology introduced to mitigate radiation effects has been the use of SOI that slowly spread throughout the semiconductor industry for high performance applications. To further enhance the tolerance of SOI devices to radiation effects, nitride BOX layer and use of body-ties are the prominent methods identified to harden them. This thesis also reports analysis of the effects induced by exposure to Gamma radiation on device characteristics of an extremely scaled 25 nm Q-FinFET, developed using 3D process and device simulator. Apart from radiation model, various other models are switched used in simulator to study quantum effects. The effect of irradiation on conduction band energy, threshold voltage, on-state drive current, off-state leakage current and sub-threshold slope of QFinFET have been reported. Process and device mixed mode simulations are also carried out to analyze the effect of heavy ion strike on contiguous 3D SRAM cell. We observe that multiple gate devices are more immune to radiation effects as compared to single gate devices. Flip flop and SRAM cell are one of the most vulnerable circuits to ionizing radiation. We have proposed different circuit level techniques to mitigate the radiation effects in flip flop, SRAM cell, sense amplifier and address decoder. This thesis presents novel method to make flip-flop radiation tolerant. For the purpose of validating the proposed flip-flop, simulated results have been compared with the conventional D-type flip flop and also with the reported radiation hardened flip flops. We observe that the proposed approach has significantly less overhead than approaches based on other reported radiation hardened techniques. Combinational logic block

(CLB) containing flip-flops is one of the major components in field programmable gate array (FPGA). As a case study, we have designed CLB using conventional D type flip flop as well as proposed flip flop and carried out analysis that proves the effectiveness of the proposed radiation tolerant flip-flop. Various methods to make SRAM cell immune to radiations have been discussed in the thesis. The best possible method to make SRAM cell immune to radiation has been found out. Analytical model for the critical charge has also been developed. Modified source potential based several types of SRAM cells are studied. SRAM cells are designed with pull-up and/or diode pair configuration. It was concluded that the proposed (type 5) configuration can be used to enhance the immunity to ionizing radiations. In this thesis, a novel radiation hardened SRAM cell has also been proposed that has less charge removal time and read delay. We observe that SRAM cell based on multiple gate technology gives better immunity to radiation as compared to bulk and SG technologies. Sense circuitry in the memory system is highly sensitive to radiation effects. Radiation induced upset may be directly generated in the sense amplifier itself. The occurrence of an upset in the sense amplifier produces a wrong output in the readout process, without changing the memory cell stored value. This will have serious implications on the reliability of SRAM cell. This thesis targets the memory peripherals to make them tolerant to radiations. The novel radiation hardened, independent-gate, process-variation-tolerant, high speed double gate (DG) FinFET based sense amplifier (RHIGSA) has been proposed in this thesis. The new design exploits the 'Dual Interlock Cell' (DICE) latch and the back gate of a DG FinFET device for dynamic compensation against ionizing radiations. High performance variant of RHIGSA has also been presented. Tolerance to process variations and lower sensing delay are the prominent features of the proposed sense amplifier.

Address decoder is another vital element in the memory array which realizes selection of a memory cell. In case of radiation induced fault in address decoder, address may be applied to wrong memory cells for reading or writing purpose, Multiple upsets were also observed due to a fault in the disabled word line of address decoder. This thesis deals with the issues related to the effect of radiations in memory address decoders. Features of different types ofNOR address decoders based on DG-FinFET technology are presented. Various schemes based on back gate bias connections and restricted swing on enable and address lines have been discussed. Power, delay and effect of process-voltage-temperature (PVT) variations have been reported. Through this study, we observe that tied gate configuration is the best choice for radiation hardened address decoders. However, there is a trade-off involved for high performance or low power applications. Finally, we can conclude that, the use of Nitride oxide, body contact device and multiple gate structure are the efficient methods to mitigate radiation effects in MOS devices. Novel circuits for flip-flop, SRAM cell and sense amplifier, proposed in this thesis, could be used to achieve immunity against ionizing radiation.