ROBUST AND ULTRA LOW POWER SUBTHRESHOLD LOGIC: A DEVICE/CIRCUIT CO-DESIGN

Abstract

Digital circuits operating in subthreshold region have gained wide interest due to their suitability for applications requiring ultra low power consumption with low-tomedium performance such as RFID, wireless micro sensors and biomedical implants etc. One of the major concerns for subthreshold circuit design is increased sensitivity to process, voltage and temperature variations. Considerable attention has been given for analyzing superthreshold circuit behavior with progressive technology scaling, but no such attention has been given as to how subthreshold circuits would behave under such conditions, particularly using DGSOI devices with circuit co-design. This is addressed as first part of the work with detailed analysis of the effect of variations on different device parameters like gate oxide thickness, channel length, threshold voltage, supply voltage, temperature and reverse body bias on bulk CMOS devices for subthreshold operation. Acomparative study of performance and robustness between nano scale CMOS and DGSOI technologies with circuit co-design for optimal subthreshold operation has been carried out along with a comparative study of performance and robustness between bulk CMOS and tied gate (3T) and independent gate (4T) DGMOSFET device options for subthreshold logic. From the study, we conclude that DGSOI devices are better candidates in terms of performance and robustness as compared to bulk devices for both static CMOS and pseudo NMOS logic families. Static noise margin comparisons shows that the performance degradation in DGSOI pseudo NMOS logic for subthreshold design is not as drastic as in bulk MOS circuits. Comparing the effectiveness of pseudo NMOS for DGSOI circuit with respect to bulk circuit at a supply voltage of 200mV, DGSOI circuits have - 80% better NMl value and 52% better Vm value than equivalent bulk CMOS based subthreshold circuit. Robustness comparisons of bulk CMOS and DGSOI circuits for subthreshold logic with regard to PVT variations demonstrate that DGSOI circuit has 40 % lower power sensitivity, 34% lower delay sensitivity and overall PDP variation is 47% lower compared to equivalent bulk CMOS circuit for temperature variations and 51%, 49% and 75% lower respectively for supply voltage variations. It has been further observed that fluctuations in temperature have not much effect on SNM values of a DGSOI inverter, but has significant effect on standby power, where as supply voltage and threshold voltage fluctuations have severe effect on inverter SNM values and standby power and thus limiting ultra low power memory applications. Few papers support the superiority of symmetric double gate (SDG) than asymmetric double gate (ADG) devices (due to their excellent gate control over channel, near ideal subthreshold slope, almost double Ion, better variation tolerance etc). Similarly, there are quite a few papers supporting the possible superiority of ADG devices (due to their dynamic threshold voltage lowering, which enable low Ioff and high Ion, with low gate capacitance and at the circuit level offer much design flexibility and options for circuit designers). So, it is not very clear at this stage, whether SDG or ADG devices will be better suited for optimal subthreshold circuit design. This is addressed as second part of the work with consideration of four device DGMOSFET device options such as 3TSDG (tied gate symmetric DG), 3TADG (tied gate asymmetric gate oxide DG), 4TSDG (independent gate symmetric DG), 4TADG (independent gate asymmetric gate oxide DG) for subthreshold operation. For circuit co-design, logic families such as static CMOS, pseudo NMOS, Domino, CPL, DCVSL and DCVSPG etc, have been considered along with above 4 DGMOSFET n device options to come up with robust and energy efficient subthreshold circuit design. It has been observed that EDP shows to be a better subthreshold performance metric than PDP. It has been seen that EDP for 4T configuration is substantially higher as compared to 3T configuration, which proves that for better overall subthreshold logic performance, it is preferable to use 3T as compared to 4T configuration. The 3TSDG configuration has around 78% better EDP value than 4TSDG configuration. Combinational circuit's Power, Delay and PDP comparisons of 3TSDG, 3TADG, 4TSDG and 4TADG options for subthreshold Logic reveal that 3TADG circuits have approximately 13-14% better power consumption than 3TSDG, 4-5% better speed and 16-18% better PDP than 3TSDG based circuits. Comparisons clearly show the very poor power, delay and PDP performance of 4T option than 3T option for subthreshold logic, particularly as complexity of circuit increases. From the results, we can conclude that ADG is a better design option than SDG both for 3T and 4T options, although less effective for 4T option in comparison to 3T option for subthreshold logic. When EDP is taken as a subthreshold logic performance metric, independent gate option with asymmetric feature for DGMOSFETs shows to be better for robust subthreshold logic gates. Where as in presence of ±10% variations in temperature, all performance metrics shows the effectiveness of independent gate option with asymmetric feature as optimal for robust subthreshold logic. Thus, overall, independent gate option (4TSDG) is -65% more robust than tied gate option (3TSDG) for symmetric case, and -75% more robust for asymmetric case for subthreshold logic. Within independent gate option, asymmetric option shows to be -26% more robust than symmetric option for subthreshold logic. in From the logic families comparison for robustness, it can be observed that for tied gate option, sub- CMOS, sub-Domino and sub-DCVSL have almost similar and better energy consumption and robustness characteristics with respect to PVT variations and even sub- Domino and sub- DCVSL have better performance than sub- CMOS and could be thought of as good alternatives for sub- CMOS for subthreshold logic. For independent gate DGMOSETs for subthreshold logic with various circuit topologies, Pseudo nMOS has comparable overall performance with other logic families unlike for tied gate option. Although sub- CPL and sub- DCVSPG are poor in terms of energy consumption, but better robustness in terms of less function failure rate has been demonstrated in comparison with other better logic families option for 3TDG option and in this case, sub- CPL has shown better robustness for 4TDG MOSFETs subthreshold logic circuits. Third part of the work address the development of analytical models for 3T-4T DGMOSFETs which will be helpful in the compact model development for DGMOSFETs. Of the various analytical models proposed so far for SDG and ADG devices for subthreshold operation, some are either 1-D models or 2-D models only with SDG or 2-D models with all options, but not covering underlap feature of DGMOSFETs. To the best of our knowledge no single analytical model for DGMOSFET subthreshold operation has been proposed which include symmetric, asymmetric, tied and independent gate options with an underlap feature. In this work a new analytical potential model for DGMOSFET's gate overlap and underlap regions satisfying above mentioned features has been proposed and validate its accuracy with the reported models and numerical simulations. Using the proposed potential model, underlap DGMOSFET threshold voltage, threshold voltage roll off, DIBL,

subthreshold current and subthreshold swing are modeled and validated with reported models, experimental data and TCAD device simulations for few cases. Proper tuning of the back gate voltage (independent gate operation) with almost negligible adjustment of device geometries such as Lg, tsj, tbox has been observed for minimizing threshold voltage roll off. It has been further observed that increasing the gate underlap to an optimal value is a better technique than reducing body thickness for effective tuning of DGMOSFET device threshold voltage minimizing SCEs due to threshold voltage roll off and DIBL etc. Another significant observation is that increasing gate underlap length increases the device threshold voltage and beyond an optimal gate underlap value, there is no significant effect. It can also be observed that as back gate insulator is made more and more thinner, the influence of gate underlap on device Vth has become negligible. Thus, for underlap to be effective, the back gate insulator should not be made too thin. Overall, the model shows that gate underlap feature and asymmetry brought in device by proper tuning of back gate bias, back gate oxide thickness and gate work function materials add more flexibility for tuning of DGMOSFET device threshold voltage values which are not available in tied gate and symmetric DGMOSFET threshold voltage models. It has been demonstrated how device subthreshold leakage current and subthreshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry, gate material work functions asymmetry in combination with optimal gate underlap length. It has been further observed that whatever reduction in subthreshold leakage current that can be brought by reducing the body thickness, the same can be done by increasing the gate underlap without reducing body thickness, showing gate underlap can be more effective than body thickness reduction for minimizing subthreshold leakage currents in underlap DGMOSFET circuits. Models demonstrate that asymmetric work function underlap 4T DGMOSFET would have better device subthreshold slope values along with increased back gate oxide asymmetry.