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|Title:||DIGITAL DESIGN AND VERIFICATION OF AHB/AXI SLAVE INTERFACE|
AHB/AXI SLAVE INTERFACE
|Abstract:||Nowadays, the integration of several system components or IP blocks, such as processors, DSP units and memories on one chip is overwhelming the industry. The method of integrating several components on one chip is known as System on Chip (SoC) design. Due to the increase of the number of the components integrating on the chip, some problems, such us inter-connection communication, system throughput and response time of the system, have been introduced. To resolve these problems the concept of Network on Chip (NoC) has been applied on the SoCs. In this project this concept is applied on the communication channel between a processor and a memory where the AMBA AXI protocol is used for the communication between these two components. In this protocol the processor (master) triggers the communication with the memory (slave) and waits for the response of the latter. The access on the bus between the two components is fixed. Bus architecture topologies enable applications spanning from low-end to high-end in embedded SoC space and core IP for external slaves. In this report design of slave IP core is presented to attain better results of Advanced Microcontroller Bus Architecture and to enable interfacing with external slaves. The slave IP core is interaction between AXI interface and generic external slave. Design process involves processing of address transfer, data transfer and control signaling through proper utilization of read and write channels. Main building blocks of AXI4 slave IP involved in design process are channel FIFOs, Request Arbiter, Exclusive Access Monitor, Finite State Machines, Address Generator. The key benefits involved in designing AXI4 slave IP are increased productivity, greater flexibility and greater IP availability. AXI4 slave IP cores are designed to interface masters with advanced features to generic slaves such as memory controllers and external memories. The ultimate approach to improve system performance is to design better core IP for external slaves making system independent of internal architecture.|
|Appears in Collections:||MASTERS' DISSERTATIONS (Electrical Engg)|
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