Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/3169
Title: DIGITAL IMPLEMENTATION OF RF DIGITAL RECEIVER ON FPGA
Authors: Chaubey, Gorakh Nath
Keywords: ELECTRICAL ENGINEERING
DIGITAL IMPLEMENTATION
RF DIGITAL RECEIVER
FPGA
Issue Date: 2012
Abstract: This dissertation report presents the design and implementation of RF digital receivers on FPGA. As the development of digitization, especially the hardware technology increases enormously, software defined radio (SDR) becomes a mainstream gradually. The thought of SDR theory is to implement all radio functions by software programming on a universal, standard and modularized platform. SDR emphasizes an opening architecture and full programmability, and new functions will be realized by software upgrade. SDR theory adopts standard, high- performance, bus-opening structure, and it is beneficial to upgrade and expand the hardware modules. According to the SDR theory, AD/DA should approach RF or IF section to digitize, and realize all receiver functions by digital signal processing. However, RF full sampling cannot be achieved because of the limitations of digital devices. RF band-pass sampling receiver has become possible to achieve due to enhancement of DSP and micro-electronics technology. In this dissertation report, general structure of digital receiver is summarized first. The second section discusses the multi-channel parallel digital down conversion (DDC). Digital signal parallel correlation processing (match filtering) and data output-interface are mentioned separately in the next sections. DDFS is for generating digital sinusoidal waveform to generate shape for the incoming bit-streams. This digital receiver has been implemented by using system generator platform and VHDL coding.
URI: http://hdl.handle.net/123456789/3169
Other Identifiers: M.Tech
Appears in Collections:MASTERS' DISSERTATIONS (Electrical Engg)

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