ANALYTICAL MODELING OF DOUBLE GATE FinFET AND ITS APPLICATIONS TO SRAM CELL DESIGN

Abstract

Transistor dimensions have been scaled down to nanoscale dimensions to enhance the driving capability and switching speed. International Technology Roadmap for Semiconductor (ITRS)-2007 report shows an industry wide consensus on the "best current estimate" of the industry's research and development needs. Silicon has taken a vital role in semiconductor industry while III-V semiconductor devices play a major role for various electronics applications. The limiting factors in the bulk MOSFET downscaling is the power consumption due to Short Channel Effects (SCEs), leakage current and subthreshold slope degradation. Novel devices are being investigated very rigorously to continue the scaling trends. In the device research community, researchers are looking for such a device which has low leakage and low threshold voltage without compromising on performance, resulting in multiple gate structures. Such examples are the Double Gate MOSFET and FinFET device. A self aligned Double Gate (DG) FinFET reduces leakage currents, process parameter variations and also eliminates short channel effect. This thesis deals with modeling and simulation of FinFET device and subsequent application to the design of FinFET based 6T-SRAM cell as well as analysis of design issues and performance metrics. In this thesis, an extensive literature survey of the state of the art in the area of study is presented. Many important research papers are referred and cited which allows one to fully appreciate the usefulness ofsuch novel devices in present day circuits. Various research gaps are also investigated. One dimensional potential modeling of single or double gate MOSFET is not enough to explain its various physical facts within the device in nanoscale regime. At extremely low dimensions, electric field in both longitudinal and transverse directions becomes substantially large. Hence, two dimensional (2D) device modeling is required to enhance the accuracy of the results. 2D models gives a more accurate result but at the cost of the computation time. The Quantum Mechanical (QM) analytical modeling of potential for the FinFET device under study carried out. This gives closed form solution of surface potential. Further, the threshold voltage evaluation becomes an important issue in order to undertake power dissipation characteristics. Hence extractions of threshold voltage and parasitic source/drain resistance modeling have been also carried out in order to understand the switching behaviour of the device. Various potential profiles such as surface potential, front gate to back gate potential, source to drain potential and 3D potential plot for the FinFET device under study have also been presented. Key issues including FinFET device structure, design parameters, potential modeling, process parameter variation effects and device scaling limit have been undertaken quantitatively as well as qualitatively. The results obtained on the basis of our proposed analytical model have been compared and contrasted with the reported experimental results and a close match was found. The analytical modeling for Quantum mechanical (QM) inversion charge, field dependent mobility and drain current for nanoscale Double Gate (DG) FinFET have been evaluated. As the device dimensions are excessively reduced and the dimensions of the device becomes of the order of the de-Broglie wavelength of electron, it is imperative to undertake an extensive Quantum Mechanical (QM) modeling for the device under study. An extensive analytical modeling of FinFET

device has been carried out for extracting QM inversion charge. Analytical model has been developed to estimate the drain current. Further, variation of drain current with various process/device parameters is carried out for the FinFET device structure under study. The effect of fin thickness (Tfin) and fin height (Hfin) on drain current has been modeled and discussed. In order to evaluate the output drain current, a comprehensive mobility model for the charge carriers has been carried out. Various mobility models have been studied and implemented during the course of work and appropriate mobility model is taken up in order to evaluate the drain current. The results obtained on the basis of our model are compared with our TCAD Sentaurus simulation result as well as reported experimental results for the purpose of validation. The analytical modeling and estimation of various types of leakage currents associated with the FinFET device are presented, as low leakage devices are required for low power consumption for various applications. The various leakage current components in FinFET device have been evaluated such as subthreshold leakage current, gate tunneling leakage current and its dependence on various device/process parameters. The subthreshold leakage current is primarily due to diffusion of carriers and has been modeled analytically. Gate to channel leakage is primarily due to tunneling of electrons from inverted surface channel to gate. We have also analytically calculated subthreshold swing for FinFET to evaluate the subthreshold leakage current. As the device dimensions are reduced, the off state leakage current substantially increases because of many QM effects. This result in larger power dissipation of the device and the matter assumes critical importance in SRAM, as FinFET SRAM designs are prone to larger power dissipation. The results obtained have shown that at same technology node, the leakages in FinFETs are lower as in compared to DG-MOS devices. Further, our analysis shows the improvement in the performance due to reduction in leakage current of FinFET device. It can be appreciated that the devices by themselves don't add to the existing integration era. But until, a circuit analysis using the proposed devices is undertaken, the full benefits of integration cannot be captured. Logic and memory circuit design in nanoscale regime requires control over leakage currents with device level parameter variations. FinFET based 6T SRAM cell design using device/circuit co-design approach also carried out. Our analysis shows that use of FinFET devices with intrinsic body doping reduces leakage current and short channel effects. Hence, we conclude that FinFET devices can emerge as one of the promising candidate for reducing leakage components with minimum body transition time, making it efficient for low power and high performance circuit design in nanoscale regime. Further, FinFET based SRAM cell usually uses the smallest device on chip packed very closely together to achieve high density. Thus they are more sensitive to process variations. The FinFET based 6T SRAM cell uses cross coupled inverter structure to store bits. The mismatch between cell devices can cause data flipping during read operation. Thus the primary goal ofthe proposed design includes maximizing stability and minimizing leakage in SRAM, besides achieving maximum density. Design considerations for maximizing performance and yield of FinFET-based 6-T SRAM at the 32 nm have been examined. It is shown that, FinFET based SRAM cells have enhanced performance over planar bulk-Si MOSFET SRAM cells. Our proposed FinFET based 6T-SRAM cells have improved the 'read' and 'write' margin, without compromising on the area requirement. The simulations have been carried out in HSPICE with appropriate structuring of model file containing various device

parameters both independent and extracted. The analysis for the performance metric of FinFET based SRAM cell such as SNM, RNM, WNM, power, delay have been also carried out. Our analysis shows that, use of FinFET device with intrinsic body reduces leakage current and enhances the driving capability. Hence, we conclude that FinFET can emerge as one of the promising candidate for reducing leakage components making it efficient for low power and high performance SRAM cell design in nanoscale regime.