DIGITAL DESIGN AND VERIFICATION OF AHB/AXI MASTER INTERFACE

Abstract

With its unique properties, AMBA AXI-4 bus interface can utilize the resources of FPGA efficiently. Objective of the latest generation AMBA interface are to be suitable for high-bandwidth and low-latency designs, to enable high-frequency operation without using complex bridges, provide flexibility in the implementation of interconnect architectures. The AMBA AXI-4 system consists of master, slave and bus. During each transaction the address/data to be read/written is initiated by the master, the slave responds accordingly. AMBA AXI-4 Master interface can support multiple masters and multiple slaves interfacing, with single master single slave talking to each other at a time. Arbiter avoids the collision, when two masters initiate the transaction at a same time. AXI masters and slaves are connected together through a central interconnect, which routes master requests and write data to the proper slave in case of writing the data, and returning read data to the requesting master in case of reading the data. The interconnect also maintains ordering based on tags if, for example, a single master pipelines read requests to different slaves. In the present work single master to single slave interfacing has been designed, where master can access the number of memory locations for reading and writing the data. The design has been verified by performing the simulation and the results obtained have been discussed. It is modelled in VHDL & design process is done using the Xilinx ISE (Integrated Simulation Environment) platform and FPGA implementation is targeted.