ANALYTICAL MODELING OF LOW LEAKAGE MGDG MOSFET AND ITS APPLICATION TO SRAM

Abstract

Semiconductor industry is approaching towards the end of technology roadmap as the device dimensions are shrinking. Novel device structures are being investigated to follow the scaling trends of International Technology Roadmap for Semiconductors (ITRS). Various modifications at circuit level have also been carried out in order to meet area constraints and power budgeting limitations. Due to downscaling of single gate bulk MOSFET, power consumption increases due to short channel effects (SCEs) including threshold voltage roll-off and subthreshold slope degradation. Such effects increase the leakage current associated with the device hence increases the power consumption. Hence, emerging research device (ERD) community is looking for such a device with low threshold voltage, low leakage and high performance. This results in multiple gate structure such as Double Gate (DG) MOSFET. Double Gate MOSFETs are classified broadly into two categories as; Asymmetric Double Gate (ASDG) MOSFET: asymmetric nature of the device can be obtained with different work functions for both front and back gates, different insulator layer thicknesses and different gate potentials applied on both the gates. Symmetric Double Gate (SDG) MOSFET: a symmetric type DG MOSFET with both the gates having identical work functions, identical insulator layer thicknesses and same applied gate potentials. Another class of DG MOSFET is Metal Gate Double Gate (MGDG) MOSFET, which is used for ultra low power consumption circuits with gate as metal and with intrinsic channel doping. MGDG offers various advantages: metal gate eliminates poly depletion effect and eliminates threshold voltage fluctuations. Subthreshold current is reduced due to less DIBL and reduced short channel effects, because of absence of bulk charge in channel. Hence negligible surface electric field causes lower gate to channel leakage and intrinsic body doping eliminates random dopant fluctuation. Further, electric field at the edges as well as interface is reduced which results into a decrease in edge direct tunneling current [116]. Midgap metal gates are easier from fabrication perspective but reduces the performance hence dual metal gates are required for improved performance. In our current work, we have proposed a dual metal gate device with ultra thin Aluminum Nitride (A1NX) buffer layer with Hafnium (Hf) as gate metal with work functions of 4.4 eV for n-channel device. Because of equal applied potentials on both the gates, symmetric word is associated with the proposed device, known as Metal Gate Symmetric Double Gate (MG-SDG) MOSFET. One dimensional potential modeling of single of double gate MOSFET is not enough to explain its various physical facts within the device in nanoscale regime. At extremely low dimensions, electric field in both longitudinal and transverse directions becomes substantially large. Hence, two dimensional (2D) device modeling is required to enhance the accuracy of the results. 2D models gives a more accurate result but at the cost of the computation time. Ways and means should be found out both at modeling as well as architectural level in order to reduce the computation time without compromising on the accuracy of the result. In this thesis, 2D analytical potential modeling, inversion charge density modeling and drain current modeling is carried out for nanoscale MG-SDG MOSFET and Midgap Symmetric Double Gate (SDG) MOSFET through the evaluation ofquantum surface potential. 2D analytical potential modeling is carried out first for Asymmetric Double Gate (ASDG) MOSFET and then modeled for SDG MOSFET with ultra thin body (UTB) device

with boundary values which are based on the physics of the device. Center and surface potential is modeled analytically in this thesis below threshold voltage while in the post threshold voltage, it has been modeled using 2D ATLAS device simulator. Quantum mechanical corrections (QMC) are applied for the purpose of modeling of potential, inversion charge density and drain current through threshold voltage. Variation of threshold voltage with various device parameters is evaluated. Variation of surface potential and inversion charge density is carried out with gate to source voltage. A shift in surface potential due to Quantum Mechanical (QM) approach is observed as compared to classical model. Variations of inversion charge density and drain current are carried out with various device parameters. For the purpose of verification and validation of our proposed model, we have compared and contrasted the results obtained through our model and the results obtained through 2D ATLAS device simulator. Low leakage devices are required for low power consumption for various applications. The work function engineering alters the threshold voltage of the nchannel MG-SDG for low power high performance nanoscale circuit design with Hf/A1NX as gate metal using both conventional (Si02) and high-k dielectric (Si3N4). We have chosen Hf/A1NX as gate metal because ofits optimum threshold voltage and leakage currents. Further, our analysis shows the improvement in the performance due to reduced threshold voltage and reduction in gate leakage current with Si3N4 as gate dielectric. We have analytically calculated subthreshold slope and ideality factor for MG-SDG MOSFET to evaluate the subthreshold current. The electric field modeling across an insulator layer is carried out for the modeling of gate to channel leakage current and edge direct tunneling leakage current. The local electric field is modeled from the developed 2D potential modeling for the estimation of band to band in tunneling current. Asubstantial reduction in all the leakage components for the device under study with respect to currentDG devices is obtained. It can be appreciated that the devices by themselves don't add to the existing integration era. But until, a circuit analysis using the proposed devices is undertaken, the full benefits of integration cannot be captured. Logic and memory circuit design in nanoscale regime requires control over leakage currents with device level parameter variations. MGDG MOSFET has been proved to be vital in nanoscale regime for its leakage reduction with appropriate back gate bias and reduced sensitivity to process parameter variations. Super coupling effects are considered for evaluating leakage currents with back gate bias for both conventional (Si02) and high-k dielectric (S13N4). The proposed DG device/circuit co-design successfully demonstrates the benefit of using independent gate devices which significantly reduces leakages in Static Random Access Memory (SRAM) architecture while minimizing the latency time. Effect of back gate bias on front channel electrical properties is modeled through variation in front channel threshold voltage. In our design, we typically used forward biased back gate devices in critical path during active operation to improve performance and switch to negative back gate bias during standby mode to reduce leakage. From analysis, it has been found that at aback gate bias of -0.4V, most of the leakage currents are minimum. Except BTBT current, all leakage currents will increase monotonically with back gate voltage from -0.4V to 0.4V. But its value becomes very low as compared to other leakage components. Gate to body capacitance becomes minimum in DG MOSFET's with intrinsic body, so we can exploit this feature for minimizing the latency time with back gate bias in MGDG MOSFET for robust circuit/memory design in nanometer regime. Our analysis shows that use ofMGDG devices with intrinsic body reduces latency introduced by body

biasing mechanisms for leakage reduction. Hence, we conclude that MGDG MOSFET can emerge as one of the promising candidate for reducing all leakage components with minimum body transition time making it efficient for low power and high performance circuit design in nanoscale regime.