PERFORMANCE ANALYSIS OF STAGE-REROUTING SWITCHES FOR ATM NETWORKS

Abstract

Asynchronous Transfer Mode (ATM) is widely accepted as an effective way of carrying information of broadband services in Broadband Integrated Services Digital Network (B-ISDN). There has been an enormous effort on the design and implementation of fas': packet switches suitable for ATM. Among the switching architectures proposed, multistage interconnection network (MIN) based switches, such as Banyan networks, are attractive for their simple routing scheme, low hardware complexity, regular structure, and ability to deliver multiple packets simultaneously. Although MINs are the most desirable building blocks for switches, their shortcomings remain blocking and hence throughput limitations. A large number of techniques have been proposed to reduce/eliminate blocking. Buffering concepts, sorting, using multiple links between switching elements (SEs), placing multiple networks either in tandem or in parallel, increasing number of stages, and speeding up the internal links are the few techniques proposed to resolve blocking and hence to improve the throughput of Banyan type switches. In this thesis work an effort has been made to design an ATM switch architecture whose throughput can be enhanced by increasing the number of stages. For this purpose, high speed SEs available in the literature are used. Further, the number of stages has been optimized to achieve a desired performance. The following four architectures are proposed/studied as an outcome of this work :

* Omega Rerouting Switch (ORS) Tandem Stage Switching Fabric (TSSF) High Speed Tandem Stage Switching Fabric (HSTSSF) * New Stage Rerouting Switch (NSRS) The performance analysis of all these architectures has been carried out. The performance analysis includes maximum throughput, cell loss probability and average delay per cell. The analysis is performed using uniform (Independent Bernoulli Process) and non-uniform (bursty and hot-spot) traffic models to cover the wide range of broad-band services. The routing and interconnection algorithms are developed for each of these switches. For one switch of size 64 x 64, extensive study is presented.