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| Issue Date | Title | Author(s) | Research Supervisor/ Guide | Type |
|---|---|---|---|---|
| May-2018 | PROCESS INDUCED MECHANICAL STRESS AWARE CMOS CIRCUIT DESIGN | Sharma, Arvind Kumar | Bulusu, Anand | Thesis |
| Sep-2015 | MODELING AND SIMULATION OF DOUBLE GATE TUNNEL FIELD EFFECT TRANSISTOR (DG-TFET) | Menka | Dasgupta, Sudeb; Bulusu, Anand | Thesis |
| Sep-2014 | TIMING MODELS FOR EFFICIENT CHARACTERIZATION OF NANOSCALE VLSI SINGLE STAGE STANDARD CELLS | Kaur, Baljit | Bulusu, Anand; Manhas, Sanjeev | Thesis |