ON A DESIGN APPROACH FOR REDUCING ALIASING ERRORS AND ACHIEVING HIGHER TESTABILITY GOALS IN LFSR BASED TESTING OF COMBINATIONAL CIRCUITS

Abstract

This thesis is devoted towards enhancement of testability by reducing aliasing errors in BIST environment. Towards this direction of achieving higher testability goals, mechanisms which effect the fault-coverage when an LFSR based technique is used have been critically examined, and based upon the analysis and critical assessment a design approach has been postulated. The proposed design approach is the result of a two-pronged study of the effectiveness of LFSR based testing technique. Firstly the behaviour of characteristic polynomials and polynomial seeds with respect to aliasing errors has been observed. Secondly, simultaneous use of different test-pattern generators and response data compressors and their impact on the effectiveness of the technique is viewed. For examining the issues involved in the first part of the study, analysis tools have been developed and an algorithm is proposed for the determination of all possible n order primitive polynomials as well as their reciprocals. In the process of this study several results, unique in the area of LFSR based testing of digital circuits, have been observed. Theoretical investigations have also been included to validate these observations. As a result of the second part of the study, a unified built-in testing scheme has been proposed to make the LFSR based testing of combinational digital circuits more effective. A proposal for implementing this scheme has also been presented in this thesis.