Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/2342
Title: T.CAD EVALUATION OF FIN ARCHITECTURE ON SOI SUBSTRATE AND ITS COMPARISON WITH PLANAR FDSOI 'MOSFET AT 28nm TECHNOLOGY NODE
Authors: Sahu, Prahlad Kumar
Keywords: MOSFET;TCAD;28NM;ELECTRONICS AND COMPUTER ENGINEERING
Issue Date: 2013
Abstract: In this report, we report the TCAD Simulations of 28nm FDSOI MOSFET calibrated against the silicon data at 28nm FDSOI technology. We further extend our simulations to find the effect of Fin architecture in SOI substrate. The effect of sidewalls inclination of the Fin is also studied to emulate the real fabrication process. All these three MOSFET architectures are DC comparison against various device parameters like Off-Current, On-Current, threshold voltage Subthreshold Slope and Drain Induced Barrier Lowering. For transient analysis we had done work in the field of ESD (Electrostatic Discharge) and also done search for ETICS effect in FDSOI which is recently reported in FinFET. ESD characteristics of Bulk MOSFET, FDSOI and FinFET devices are presented and compared. ESD setup is made using TOAD simulator to implement ESD event in virtual device structure mentioned above. To understand the physics behind the ESD event in Depth. We had investigated effect of gate on the avalanche breakdown and the turning on of the inherent BJT in device. Recently a new phenomenon named as "Extension Transistor Induced Capacitance Shielding (ETICS)" is reported in FinFET [2]. In this phenomenon the FinFET extension region forms a parasitic transistor which shields gate-extension fringing field capacitance. It explains how parasitic fringing field varying with the applied gate voltage effect input and parasitic capacitance of device. This effect depends on low doping profile of device under the spacer region as well as on the spacer length and its relative permittivity. We are evaluating the existence of ETICS in FDSOI. Due to this. phenomenon, we observe a strong dependence of effective values of FDSOI logic gate capacitances on transition times of their terminal voltages, which is unlike the conventional transistors. It is required to modify the delay estimation methods by including ETICS for accurate FDSOI circuit design.
URI: http://hdl.handle.net/123456789/2342
Other Identifiers: M.Tech
Research Supervisor/ Guide: Sithanandam, R.
Bulusu, Anand
Dasgupta, Sudeb
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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