CROSSTALK AVOIDANCE IN RLC MODELED INTERCONNECTS USING LOW POWER ENCODER

Abstract

Most of the encoding methods proposed in recent years have dealt with only RC modeled VLSI interconnects. In deep sub-micron (DSM) technologies, on-chip inductive effects have increased due to increasing clock frequency, decreasing signal rise times and increasing length of on-chip interconnects. This issue is a concern for signal integrity and overall chip performance. Therefore, this thesis introduces an efficient bus encoder using Bus Inverting (BI) method. This. method dramatically reduces both crosstalk induced delay and power dissipation in RLC modeled circuits. The lower power consumption makes the proposed encoder suitable for current high-speed low power VLSI interconnects. The proposed method extends bus invert method for 4, 8 and 16 bit lines which is found to be more efficient than the existing encoders.