MEMORY TESTING SCHEME FOR FinFET BASED SRAM CELL

Abstract

The process technology scaling and push for better performance enabled embedding of millions of Static Random Access Memories (SRAM) cells into contemporary ICs. As the process technology continues to scale deeper into the nanometer region, the stability of embedded SRAM cells is a growing concern and so does the testing time. Conventional MOSFETs are no longer giving better performance as the technology is scaling down due to increased Secondary Channel Effects (SCE's), leakage currents and process variations. Here, in this work, we replace conventional MOSFET with Double Gate MOSFET (DGMOSFET) for better performance. Conventionally replace 6T SRAM cell has improved SNM of 200mV and reduced leakage currents. As the size of SRAM and functional faults increasing testing time also increasing drastically. In order to improve the testing time and efficiency we are replacing the conventional Voltage Sense Amplifier (VSA) with Current Sense Amplifier (CSA) with a sensing delay of 100ps. With the help of this CSA we are fmding functional faults (Stuck-At faults) for a single memory cell and extending this to implement MATS algorithm to a 16 bit memory size. Finally, we are proposing a algorithm to fmd Stuck-At faults (SAF) using CSA which reduce the conventional testing time and efficiency.