MECHANICAL STRESS AWARE GATE TIMING MODEL FOR COMBINATIONAL LOGIC CELLS

Abstract

The scaling of CMOS technology has led to high speed, high density integrated circuits but every successive generation has given rise to new design challenges. Accurate modeling of cell libraries has become an extremely important and challenging task for accurate timing, power and noise analysis of modern deep sub-micron designs. On account of several drawbacks like inability to deal with complex loads and non-ideal inputs present in the existing methods for characterization of standard cell libraries, the focus has shifted towards CSM (Current Source Modeling), which is preferred due to its independence with input signal shape and output load complexity. However characterization of cells using CSM is time consuming as the number of model parameters used in CSM is higher than in other methods. The standard cell libraries are characterized using currently available PDKs (Physical Design Kits). However, the device models are updated to account for the new effects observed and revision of the PDKs demands re-characterization of cells. Also requirement of a cell library at different PVT corners calls for re-characterization. This re-characterization of cells, especially with the use of CSM is very laborious. In this work we discuss in detail the method of CSM and we propose a model for the current source parameter of the CSM of an inverter with a region of validity, which can predict the change in current source parameter with number of fingers and with change in PVT corner or a model parameter. Thus the problem of re-characterization can be addressed.