A CIRCUIT DESIGN FOR ROBUST SRAM COMPUTE-IN-MEMORY ARCHITECTURE

Abstract

Artificial intelligence (AI) and machine learning (ML) are revolutionized technologies widely adopted to solve real-time problems such as speech recognition, facial recognition, cancer detection, and image classifications. Deep convolutional neural networks (CNNs) have succeeded exceptionally in AI/ML tasks. The CNN models have intensive multiplication and accumulation (MAC) computation and require ample memory space to store the pre-trained models. Therefore, they consume large amounts of power on traditional computing systems, restricting their implementations to resourceconstrained edge devices. The conventional computing system has limited memory bandwidth due to slow memory access time and consumes more power during the data movement between the processor and memory. This is known as the “Von-Neumann bottleneck.” Thus, there is a need to build domainspecific hardware primitives for energy-efficient and high-speed ML processing at the edge. Computein- memory (CiM) is an alternate hardware solution to overcome the limitations of traditional computing systems. The CiM enables the memory to perform the computations inside the memory array, where the data is locally stored. Therefore, CiM improves the energy-efficiency of the computing system by reducing the data movement between the computation unit and the memory array. The CiM also allows parallel computing, an inherent characteristic of the CNN. This thesis aims to explore the SRAM-based compute-in-memory architectures because SRAM technology is more mature and easily integrates with modern System On Chips (SoCs). First, in this thesis work, robust SRAM bit-cells have been developed and designed to support compute-in-memory 1-bit XNOR and accumulation (XAC) operation for binary neural networks (BNNs) and multi-bit MAC operation for CNNs. The proposed 10T1C SRAM bit-cell is robust and provides full-swing output in computation mode. The 10T1C XNOR SRAM bit-cell performs the inmemory 1-bit XAC operation without pre-charging the larger bitline capacitances and significantly reducing energy consumption per XAC operation. As a proof of concept and to show the application of the proposed 10T1C SRAM bit-cell, a small BNN has been implemented using 10T1C SRAM bitcell in compute-in-memory XNOR mode. The functional verification of BNN implementation was done through simulations using 65 nm CMOS technology. The proposed XNOR and accumulation (XAC) scheme is energy-efficient and achieves a high compute signal-to-noise ratio (CSNR). The achieved 1ns of latency and 2.36 fJ of energy consumption per XAC operation are (7.2×, 7.2×) and (2×, 1.31×) lower than state-of-the-art digital and analog compute in-memory (CIM) XAC schemes respectively. The proposed XAC design achieves an 8.6× improvement in figure-of-merit (FoM) over the prior stateof- the-art. Moreover, the (σ/μ) average of 0.2% from Monte Carlo simulations shows that the proposed XAC scheme is robust against systematic mismatch and process variations.