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|Title:||FPGA IMPLEMENTATION OF MEMORY-SPEED OPTIMIZED ARCHITECTURE OF 2-D DWT FOR IMAGE COMPRESSION APPLICATIONS|
|Keywords:||IMAGE COMPRESSION;OPTIMIZED ARCHITECTURE;DISCRETE WAVELET TRANSFROM;ELECTRONICS AND COMPUTER ENGINEERING|
|Abstract:||Wavelet Transform has been successfully applied in different fields, ranging from pure mathematics to applied science. Numerous studies, carried out on wavelet Transform, have proven its advantages in image processing and data compression and have made it a basic encoding technique in recent data compression standards as well as for multi-resolution decomposition of signal and image processing applications. Pure software implementations of the Discrete Wavelet Transform (DWT), however, appear to be the performance bottleneck in real-time systems in terms of performance. Therefore, hardware acceleration of the DWT has become a topic of recent research. During the compression of image using 2-Dimensional DWT (2D-DWT) two filters are used, a highpass and a lowpass filter. As these filter coefficients are irrational numbers, it is suggested that they should be approximated by using binary fractions. The accuracy and efficiency with which the filter coefficients are rationalized in an implementation impacts the image compression and critical hardware properties such as throughput and power consumption. A high precision representation ensures good compression performance, but at the cost of increased hardware resources and processing time. Conversely, lower precision in the filter coefficients results in smaller, faster hardware, but at the cost ofpoor compression performance. This thesis is aimed at development of memory-speed optimized, multiplierless architecture of 2-D DWT based on biorthogonal Daubechies 9/7 filter bank for signal decomposition. Interlacing, parallel processing and optimized shift-add operations for multiplications are used to reduce memory requirement as well as increase speed of computation. The advantages of the proposed architecture include very simple hardware complexity, regular data flow and low control complexity. Implementation of this architecture is suitable for new Xilinx Spartan-II FPGAs that offer enough memory on the chip for storage of intermediate results. The different units are simulated, synthesized and optimized for FPGA chips using Xilinx® design tools at an operating frequency well above 100MHz. Besides this low complexity architecture ensures 100% hardware utilization. With this technique, 2-D DWT can be implemented by data rearrangements, achieving the low memory required to implement being of 0(N).|
|Research Supervisor/ Guide:||Saxena, A. K.|
|Appears in Collections:||MASTERS' DISSERTATIONS (E & C)|
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