Design and on-chip implementation of Noise-Shaping SAR ADC for ECG signal processing to Predict the Early Occurrence of Cardiovascular Diseases

Abstract

This thesis discusses the design and on-chip implementation of a 12-bit Noise Shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC). The proposed ADC architecture comprises a 12-bit switched-capacitor array, noise shaping filter, dynamic comparator and a digital control unit. The switched capacitor array includes a capacitive digital-to-analog converter (CDAC) and a sample-and-hold circuit built using bootstrap switches. The digital control unit generates the reference voltage and controls the SAR logic and the output buffer. The ADC is designed using a standard 65nm process technology node. According to the results of the simulation, the suggested ADC can convert data at a rate of 10kS/s while using just 240.5 nW of power. The simulation yielded a signal-to-noise ratio (SNR) of 76.76 dB over a bandwidth of 250 Hz. The suggested ADC is appropriate for low-frequency and low-power applications like biomedical systems and ECG monitoring.