Modeling Transistor Degradation and Aging Using the TCAD Framework

Abstract

The Performance and reliability of integrated circuits depends largely on the long-term durability of transistors, which are essential building blocks of today’s electronic devices. In this master's thesis, two significant reliability issues - Negative Bias Temperature Instability (NBTI) and Hot Carrier Degradation (HCD) are specifically discussed in the context of modeling transistor degradation and aging using TCAD framework.

The First part of the thesis focuses on NBTI, which refers to the gradual degradation of transistor performance under prolonged negative biasing and elevated temperatures. Sentaurus TCAD is used to calculate the time kinetics of interface trap generation and passivation and its contribution in threshold voltage shift (∆VTH) with negative bias temperature instability. Double interface reaction-diffusion model is used to introduce stress. The ABDWT model is used to model bulk charge traps, and the transient trap occupancy model is used to determine the charge occupancy in the generated traps.

The second part of the thesis focuses on Hot-carrier degradation which arises from the energetic impact of hot carriers on the transistor channel region. This has become a key ageing process because of the continued scaling down of CMOS devices. In order to model this, we make use of current models and simulation frameworks to depict the complex physical processes arising during hot-carrier stress. Reaction diffusion enabled TCAD computes the interface trap density initiated by carrier energy and the effect of localized charges on device parametric shift. The multistate configuration model and the capture and emission model are used in the simulation framework to ensure accurate modelling of the HCD phenomena. All the simulations are being carried out on a p-channel MOSFET.