Parasitic Extraction in GAA Nanosheet Based 3D-DRAM & its Impact on Circuit Performance

Abstract

Monolithic 3D-DRAM is a method that increases memory density and lowers costs without relying on the requirement to shrink DRAM transistor feature sizes or use sophisticated and pricey lithographic procedures to produce smaller transistors. There are two methods for creating 3D-DRAM. Our explanation will centre on the first way, which includes vertically stacking several layers of memory monolithically inside of a single die. The second method joins various dies together by utilising sophisticated 3D assembly techniques, such as "Through silicon vias (TSVs)". The monolithic 3D-DRAM has the advantages of cost efficiency and high bandwidth compared to the same generation 2D-DRAM. Further, the performance and reliability of DRAM depend on its Parasitics. In this work, we proposed and simulated the entire monolithically stacked 3D-DRAM device and found its parasitic resistance and capacitance. Further, we find the variation in parasitic resistance and capacitance as a function of device dimensions like spacer length, channel width and channel thickness. We also study the effect of interlayer distance, i.e. word line to word line distance, on parasitics. Later to scale our 3D-DRAM array, we simulated and proposed total bit-line parasitic capacitance as a function of the number of memory layers and total word-line parasitic capacitance as a function of the number of cells for a common bit-line monolithic 3D-DRAM array structure. For the purpose of memory array simulation, we took 192-bit, 3 layer and 320-bit, 5-layer 3D-DRAM memory array design, in which each layer is of 64 bits, which is further divided into four banks, each with 16 bits, for both 3-layer and 5-layer circuit architecture. In each structure, we placed the layers of the DRAM array on top of the bottom most layer, which consists of total control circuitry, which includes peripherals required for all layers to achieve the area and cost-efficiency. We modelled interconnection between layers as RC and did simulate by taking parasitic R and C values that we get from device simulations. We then study the effect of number of layers on delay in reading and writing from memory.