A Methodology for Implementation of Multi-Bit Compute-in Memory Architecture in Analog Domain

Abstract

Deep neural networks (DNNs) are playing a very crucial role in many AI/ML applications, Convolutional neural network (CNN) is a DNN primarily used for applications like image classification, speech recognition, automated vehicles etc. Present day many CNNs are achieving a very high accuracy rate better than human vision but these networks are complex and thus are computationally very intensive. The traditional Von Neumann systems because of the memory wall problem are not the suitable ones for these architectures to be implemented on. Thus, many recent works approached compute in memory (CIM) to alleviate the Von Neumann bottleneck and perform the fundamental operation of CNN: MAC (multiply and accumulate) in the memory itself which eliminates the huge power consumption for data movement between the memory and CPU. Additionally, CIM has an advantage of parallel computing capability which is an inherent property of CNN computing, since all the operations in CNNs are massively parallel and regular in nature In this project, we present a 64x64 9T1C SRAM macro for bit wise multiplication and bitline charging scheme for the accumulation. The binary weighting for the weights is achieved by C-2C ladder network. An optimized 4b flash ADC is used as the analog readout circuit. The proposed architecture performs 1024 MAC operations between activation input(4b) and weight(4b) in a cycle. This work achieves a throughput of 455 GOPS, energy efficiency of 1013TOPS/W at 222MHz frequency maintaining a very high signal margin of 53.8 mV. This proposed work is implemented on 28nm Technology node at 0.9 V supply.