Impact of Device Level Variability on Aging Aware STA Methodology for Path Level Timing Estimation for Digital Circuits

Abstract

The downsizing of CMOS technology is becoming more and more of an issue in terms of circuit lifetime reliability. Transistor aging caused by bias temperature instability (BTI) and hot carrier injection (HCI) is a major concern, leading to increased threshold voltages in CMOS devices and impacting circuit timing. Accurately estimating delay using nonlinear delay models (NLDM) is a major challenge, in the current nanometer scale transistors. To address this issue, people have started using the Effective Current Source Model (ECSM), which stores predefined Threshold Crossing Point (TCP) values of the output voltage waveform with respect to different input transition time (TR) values and load capacitance (Cl). To address the aging problem, we propose a Static Timing Analysis (STA) technique based on the Effective Current Source Model (ECSM) for estimating path-level timing performance. Threshold voltage (Vth) degradation in CMOS devices is caused by time-varying mechanisms such as bias temperature instability and hot carrier injection, resulting in delay degradation in standard cells. For this, we developed a device-level variation aware timing model for a standard CMOS cell to represent threshold-crossing points (TCPs) in an ECSM .libs file as a function of stress time (t), signal probability (α), stress voltage (v), and stress temperature (T). The inclusion of stress voltage enables the analysis of the impact of aging considering net IR-drop. For a given process design kit to update TCPs in a (.libs) file as a function of stress time (t), signal probability (α), stress voltage (v), and stress temperature (T), we developed a device-level approaches for Vth degradation under various aging conditions such as static and dynamic. The proposed model has been validated and validated on various benchmark circuits using parasitic extracted netlists in Eldo SPICE environment with 28nm CMOS process technology. Finally, our model reduces the number of SPICE/stress simulations by more than 90% compared to previously reported pure simulation-based approaches.