ON DESIGNING TESTABLE BIT-SLICE ARCHITECTURE

Abstract

In this work, the problem of designing VLSI chips for testability is taken up. First considering a represen-tative functional model of 1-bit bit-slice microprocesser, a design is proposed which renders the device testable. With slightly increased pin-count and chip area, the design facilitates testing the device in lesser testing time than what is proposed in [1,151. As a second step, the design is further improvised to make the device completely self testable. The concept of 1-bit processor is extended and a design is proposed for a testable 4-bit bit-slice microprocessor.