Please use this identifier to cite or link to this item:
http://localhost:8081/xmlui/handle/123456789/2147
Title: | ON DESIGNING TESTABLE BIT-SLICE ARCHITECTURE |
Authors: | Gupta, Devendra Kumar |
Keywords: | VLSI;BIT-SLICE ARCHITECTURE;EMBEDDED SYSTEMS;ELECTRONICS AND COMPUTER ENGINEERING |
Issue Date: | 1986 |
Abstract: | In this work, the problem of designing VLSI chips for testability is taken up. First considering a represen-tative functional model of 1-bit bit-slice microprocesser, a design is proposed which renders the device testable. With slightly increased pin-count and chip area, the design facilitates testing the device in lesser testing time than what is proposed in [1,151. As a second step, the design is further improvised to make the device completely self testable. The concept of 1-bit processor is extended and a design is proposed for a testable 4-bit bit-slice microprocessor. |
URI: | http://hdl.handle.net/123456789/2147 |
Other Identifiers: | M.Tech |
Research Supervisor/ Guide: | Rai, Suresh |
metadata.dc.type: | M.Tech Dessertation |
Appears in Collections: | MASTERS' THESES (E & C) |
Files in This Item:
File | Description | Size | Format | |
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ECD178808.pdf | 4.56 MB | Adobe PDF | View/Open |
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