FPGA based Adaptive Lock-in Amplifier

Abstract

A Lock in amplifier (LIA) With adaptive input frequency capability is being proposed in this work. Lock in amplifiers have the capability to extract useful signals from an environment of heavy noise. Lock-in amplifier works with sinusoidal signals for an input frequency range of 9 — II kH z The simulation of the LIA was done in MATLAB Simulink. The simulation results show that the dual phase Lock in amplifier extracts the Amplitude Of the signal buried m noise with Signal to Noise Ratio (SNR) as small as 10dB and harmonics. While using the Lock-in amplifier for input with varying frequencies in a particular range, reference signal to be generated from the incoming signal The phase and frequency error between the reference and input signals will contribute to reduced accuracy of Lock-in amplifier system. For eliminating the phase error contributed by the higher order moving average filter and the normal multiplier phase detector, a quadrature phase detector is used in the Phase locked loop. Using this Quadrature PLL, the accuracy of the Lock-in amplifier has effectively increased in the designed frequency range. The system on-chip implementation Of the Adaptive input frequency Lock-in amplifier • is also carriedout in Altera Stratix III FPGA. Testing the implementation for noise as well as harmonics has been carried out in the proposed frequency range. Satisfac- tory performance has been given by the proposed model for each case in the designed frequency range.