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http://localhost:8081/jspui/handle/123456789/20888Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Rao, Balaga Chandrasekhara | - |
| dc.date.accessioned | 2026-05-11T05:59:48Z | - |
| dc.date.available | 2026-05-11T05:59:48Z | - |
| dc.date.issued | 2021-06 | - |
| dc.identifier.uri | http://localhost:8081/jspui/handle/123456789/20888 | - |
| dc.guide | Saxena, Vishal Kumar | en_US |
| dc.description.abstract | The recent advancement of digital technology is the re-configurable hardware i.e. field programmable gate array (FPGA), programmed by Hardware Description Language (HDL) used for high-speed applications. It has identifications for developing intelligent electronic devices, which are used in the power system components and smart grid applications i.e. fast relay for the protection of the power systems, operation and control asking high computational demand, and parallel processing. Some inherent benefit of the FPGA device is the parallelism of the hardware that increases the execution speed compared to sequential software architecture based technologies. Due to these predominant and some additional features making it more adaptable, are being considered for the protection and control through detection of faults with minimum execution time. The fault detection system on FPGA can be divided into 3 major categories- the communication module, signal processing module & relaying module. The work presented here is relaying module of FPGA based digital relays. It consists of various faults in power system network, symmetrical component analysis, different kinds of relays based on their time of operation and current vs time characteristics of IDMT relay. Followed by block diagrams of IPs generated using Xilinx System Generator. IPs developed are verified using Xilinx Vivado tool. Verification of the modules developed are carried out with sample signals and recording the simulation results that shows the proper operation of them. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | IIT Roorkee | en_US |
| dc.title | FPGA BASED DIGITAL RELAYS | en_US |
| dc.type | Dissertations | en_US |
| Appears in Collections: | MASTERS' THESES (Electrical Engg) | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 19530003_Balaga Chandrasekhara Rao.pdf | 2.02 MB | Adobe PDF | View/Open |
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