0.1-4.3 GHz RECONFIGURABLE TRANSMITTER FRONTEND DESIGN USING 130 nm CMOS TECHNOLOGY

Abstract

Communication technologies are evolving due to the demands of high bandwidth for fast and large data-sharing networks. To fulfill these demands, radio technology shifted towards multi-band and multi-standard networks. To support these upcoming (5G and beyond) and the previous (4G, 3G, 2G, etc.) standards simultaneously, the conventional transmitter architecture will become more complex, leading to a larger footprint area and high cost. To mitigate these issues, a reconfigurable transmitter frontend design and simulation has been carried out in this work for 0.1-4.3 GHz frequency range using 130nm process CMOS technology. This transmitter is suitable for these advanced technologies with a low cost and less footprint area. This reconfigurable transmitter has components like radio frequency digital to analog converter (RFDAC) and power amplifier (PA). An RFDAC directly converts a digital signal to a high radio frequency signal with less footprint area, unlike convention homodyne architecture. A High Voltage Power (HiVP) stacked PA configuration is used to increase power level by increasing voltage swing at the output by the in-phase addition of equal voltage swing at the drain-source of all FETs for wideband operation. An 8-bit RFDAC and a wideband single-stage 3-stacked power amplifier are integrated as a single chip in design and simulated using ADS software. The designed reconfigurable transmitter frontend is simulated at 2 GHz and 4 GHz frequency bands.