An Energy Efficient IOT Processor built using an Optimized Near- Threshold Voltage Standard Cell Library

Abstract

Over the last several decades, VLSI technology scaling has continued providing affordable and efficient gadgets that has significantly enriched our lives. We faced several challenges in this journey obstructing progress. These include design productivity, power consumption, and leakage issues. According to Moore’s law, abundance of transistors are continued to use for integration. But it is limited only by energy consumption. It is possible to improve energy efficiency by an order of magnitude using Near Threshold Voltage (NTV) operation. Although technology scaling continued doubling number of transistors used, reduction in supply voltage does not reduce energy per operation. The main challenge we face is to deliver logic throughput with much low energy consumption. Sub-threshold region of operation consumes much low power, but is proved to be not the most energy efficient. Comparatively, NTV region of operation provides higher energy efficiency. With energy efficient performance, there are several challenges we face at NTV. This work discusses challenges faced in sequential circuits with respect to timing margin. This work focuses on literature survey on behavior of sequential circuits Latches/Flip flops at NTV and effect on timing margins associated with it. This is an attempt to design Transmission Gate based Latch/Flip-flop at NTV considering sizing of transistors using logical effort method. Also, we tried to propose flip-flop to mitigate setup time constraint at NTV and study of some other flip-flops operating in low voltage range.