DESIGN OF HIGH-SPEED RISC-V PROCESSOR USING DYNAMIC FREQUENCY SCALING

Abstract

This research work focuses on the design of a high-speed RISC-V processor using dynamic frequency scaling (DFS). First, the RISC-V processor CV32E40P is thoroughly verified for its functionality by performing a post-synthesis timing simulation in Xilinx Vivado. The RAZOR FF is popular in timing error detection and correction. To increase the operating frequency of the processor, the RAZOR FFs are inserted in the critical path of the pipeline designs of the RISC-V processor. Two different architectures such as (1) Timing error-based DFS and (2) instruction based DFS have been designed. In the case of timing Error-based DFS, the frequency of the design is scaled up till the error signal is flagged. However, this technique suffers from short-path constraints. In the case of Instruction-based DFS, the frequency of the processor is increased or decreased based on the different types of instructions. It is found that the frequency of the processor can be changed from 45 MHz to 63 MHz based on the types of instruction executed inside the processor. Additionally, the resources required are 8140 sliced LUTs and 2585 sliced FFs which are far less than the timing Error-based DFS technique which consumed 9259 sliced LUTs and 2684 sliced FFs. The Instruction-based DFS consumed 13.7% less sliced LUTs and 3.8% less sliced FFs as compared to Error-based DFS. It is found that logical operations can run at a higher frequency such as 63 MHz compared to other complex instructions such as MAC and multiplication operations. So, we have chosen one application of ECC over the binary field which uses arithmetic and logical operations. Finally, algorithms based on Binary field multiplication and field squaring are implemented in C. The compiled machine code can effectively execute on the RISC V processor.