Dynamic Bias Latch-type Comparator in 45nm CMOS with 0.37mV input noise

Abstract

Alatch type comparator with dynamic bias pre-amplifier is implemented in 45nm CMOS process. The dynamic bias is achieved with a tail capacitor. Because of dynamic bias unlike conventional latch apmlifiers, output nodes of pre-amplifier don’t discharge com pletely. This reduces energy consumption of latch as well as recuces input referred noise of latch. First-order equation show the relation between CMOS parameters and noise. Both conventional and dynamic bias latch are compared and measurements show that dynamic bias comparator reduces the energy consumption and input referred noise level at the expense of latch delay. Keywords: Dynamic biasing;Strong inversion;weak inversion; ADC