DIGITAL DESIGN & VERIFICATION OF PHASOR ESTIMATION MODULE

Abstract

The recent advancement of digital technology is the re-configurable hardware i.e. field programmable gate array (FPGA), programmed by Hardware Description Language (HDL) used for high-speed applications. It has identifications for developing intelligent electronic devices, which are used in the power system components and smart grid applications i.e. fast relay for the protection of the power systems, operation and control asking high computational demand, and parallel processing. Some inherent benefit of the FPGA device is the parallelism of the hardware that increases the execution speed compared to sequential software architecture based technologies. Due to these predominant and some additional features making it more adaptable, are being considered for the protection and control through detection of faults with minimum execution time. The fault detection system on FPGA can be divided into 3 major categories- the communication module, signal processing module & relaying module. The work presented here is signal processing module for designing of FPGA based digital relays. It consists of filters to filter out noise, mimic filter to remove decaying DC and finally Phasor estimation technique from those fault current & voltages. The implementation of FPGA based protection and control devices can enhance various features towards making it more robust, adaptive and more reliable during abnormal conditions. Then a brief theory of various methods used in filtering & phasor estimation are discussed. Followed by block diagrams of IPs generated using Xilinx System Generator. Some discussion about the behavioral and state machine designs for the different modules discussed in the trailing part. IPs developed are verified using Xilinx Vivado tool. Verification of the modules developed are carried out with sample signals and recording the simulation results that shows the proper operation of them.