Ultra-low voltage Write Assist Technique to improve The Vmin (Minimum Operating Voltage) of SRAM Bit-cell

Abstract

Static Random-Access Memory (SRAM) is a critical component of modern semi conductor devices, providing fast access to data for CPUs and other digital circuits. As semiconductor technology scales down, the challenge of reducing the core volt age for SRAM arises. Lowering the minimum operating voltage (Vmin) is essential for power efficiency but is limited by the SRAM cell’s design and the variability in transistor characteristics.As transistors become smaller, variations in the thresh old voltage (Vth) become more pronounced, affecting stability and performance. Larger SRAM arrays exacerbate the issue as more cells mean greater susceptibility to variations and noise.The write margin is the voltage window in which a cell can reliably switch states. Reducing Vmin makes it harder to overcome the strength of the pull-up transistors during a write operation.To mitigate these challenges, write assist techniques are employed. These techniques temporarily alter the operating conditions of the SRAM cells to facilitate successful write operations at lower volt ages. Negative Bit-line(NBL) Write Assist techniques involve generating a negative voltage on the bit-lines during a write operation to improve the write margin at lower voltages. It becomes increasingly challenging to generate a negative bump on the bit-lines, which in turn restricts the functional minimum voltage (Vmin) of the system. This proposal aims to refine the write assist techniques to not only improve Vmin but also to optimize the area and performance of the system.