NEGATIVE CAPACITANCE EFFECTS IN MULTIDOMAIN FERROELECTRIC DEVICES FOR LOW VOLTAGE APPLICATIONS

Abstract

In recent decades, the burgeoning growth of mobile electronics has fueled the demand for high-speed and ultralow-power integrated circuits (ICs). Addressing this shift in computational technology requires creative solutions at both the material and device levels. Despite various strategies proposed over the last two decades to mitigate energy consumption in ICs, finding an effective and innovative solution remains challenging due to the intrinsic physical constraints of conventional complementary metal-oxide-semiconductor (CMOS) technology. Traditionally, the primary approach to reducing energy consumption in ICs has involved lowering the supply voltage. However, for CMOS field-effect transistors (CMOS FETs), this reduction comes with the trade-off of speed reduction or increased off-state leakage, attributed to the fundamental limitation of the subthreshold swing (SS) to 60 mV/decade, known as “Boltzmann’s Tyranny”. Motivated by this imperative need to curtail energy consumption in dense ICs, this thesis explores the concept of harnessing the negative capacitance (NC) effects in ferroelectric devices. The overarching motivation is to lower the supply voltage below one volt without compromising transistor performance, thereby addressing the challenge of “Boltzmann’s Tyranny” inherent in conventional CMOS FETs. Ferroelectric materials have become increasingly attractive as next-generation (beyond-CMOS) electronic device candidates because of their multidomain polarization switching characteristics. However, recent studies have predominantly focused on single-domain ferroelectricity and perovskite materials like lead zirconate titanate (PZT), which are not compatible with current CMOS technology. In this work, we present an extensive study on the NC effect in both CMOS compatible organic and inorganic ferroelectric materials, such as poly(vinylidene fluoride-co-trifluoroethylene) [P(VDF-TrFE)] and hafnium zirconium oxide [Hf0.5Zr0.5O2 (HZO)], utilizing the multidomain Ginzburg-Landau-Khalatnikov theory. Our investigation includes original ultrascaled ferroelectric gate stack designs, aiming to achieve sub-60 mV/decade operation for reducing energy consumption in ICs. Additionally, we explore various ferroelectric-based proof-of-concept devices such as Landau FET/NCFET designed for diverse applications, including passive and active voltage amplifiers, steep-slope logic devices and circuits, and mixed-signal circuit design. To facilitate this exploration, we develop several self-consistent device simulation frameworks and compact models rigorously calibrated with experimental data. The key findings of this thesis can be categorized into two main parts. Initially, we focus on introducing a robust technology computer-aided design (TCAD) modeling framework for realistic simulations of NC effects in devices utilizing organic ferroelectric materials. We also discuss calibration methodologies against experimental data, conduct sensitivity analyses on anisotropy constants, and explore non-quasistatic behaviors. The maximum switching speed of organic ferroelectric materials is predicted, and the performance of metal/organic ferroelectric/metal devices is compared with oxide ferroelectric-based devices. Following this, we concentrate on directly capturing the NC effect at an ultralow voltage with little energy dissipation in a multidomain P(VDF-TrFE) gate stack, comprehending its underlying physical mechanisms and dynamics. Additionally, we introduced a passive voltage amplifier and a stable hysteresis-free multidomain P(VDF-TrFE)-gated Landau FET/NCFET device. Simulation results demonstrate the feasibility of achieving hysteresis-free, sub-60 mV/decade operation of the Landau FET/NCFET with a minimum SS of 26.59 mV/decade. The benefits of this device are tested on digital logic circuit design, paving the way for high-speed and energy-efficient digital IC designs. In the latter part, our focus shifts to NC gate stacks using HZO ferroelectric material, outperforming alternatives like P(VDF-TrFE) and PZT with its direct CMOS compatibility and sub-10 nm scalability. We investigate the impact of HZO thickness, domain number, and process variations on HZO-device circuit co-design. This investigation provides crucial insights for optimizing designs and understanding the implications of these variations on Landau FET-based voltage amplifiers, inverters, and ring oscillators. The exploration concludes with an in-depth examination of the physical origin of the NC effect in HZO ferroelectric gate stacks. The bipolar-to-unipolar pulsing technique is employed to verify the NC effect. Predictions regarding the intrinsic switching speeds of HZO are presented, considering various polarization damping factors. The study delves into the underlying factors leading to negative drain-induced barrier lowering effects, negative differential resistance effects, and voltage amplifications observed in NCFETs. For GHz applications of the Landau FETs/NCFETs as low-power devices, the polarization damping factor should be 0.18 Ωcm to 0.22 Ωcm, or even a lesser value is desirable. This can be achieved through the reengineering of the ultrascaled ferroelectric material. A circuit-compatible hybrid compact model for leakage-aware NCFETs is developed, supporting both Landau and Preisach ferroelectric models, demonstrating the superior performance of NCFETs compared to conventional CMOS technology. The model is evaluated for various digital and mixed-signal circuit designs, such as an amplifier, inverter, 2:1 fork circuit, and ring oscillator in the Cadence Spectre environment. Our research underscores the potential of this device as a promising concept, demonstrating its ability to achieve high on-state current levels comparable to advanced CMOS technology but with a reduced supply voltage budget required for operating ICs in the more-Moore era. The ultimate goal of designing various ferroelectric gate stacks and Landau FETs/NCFETs is to expand technologies at more relaxed dimensions like bulk planar 32 nm and 45 nm nodes by improving performance and reducing power without scaling and at a lower cost than aggressive nodes. Overall, this thesis confirms that the Landau FETs/NCFETs can be used to advance NC electronics, potentially paving the way for beyond-CMOS technology.