MODELING AND ANALYSIS OF SELF-HEATING EFFECT IN ADVANCED MULTI-GATE MOSFETS

Abstract

In the era of miniaturization, the scaling of nanoscale devices has led to a complete transformation of nanoscale device structures, such as the introduction of advanced multi-gate MOSFETs like FinFETs and Stacked Nanosheet Field Effect Transistors (SNFET). However, self-heating effect (SHE) becomes a concern because of their confined channels surrounded by low thermal conductive gate oxide and buried oxide layer in substrate. The thesis investigates SHE in advanced multi-gate MOSFETs and presents novel thermal circuit, device electro-thermal models and simulation paradigms further to analyze, and optimize their thermal characteristics and related reliabilities. To this end, in the first part of thesis a thermal circuit model is developed beyond the conventional SHE circuit model to represent realistic dynamic heating between electron and lattice in SOI-FinFET device. The model considered thermal non-equilibrium phenomena established at high electric fields or frequencies in nanoscale devices and accounted heat transfer to lattice through phonon mode coupling by physically justified circuit elements that capture both electron (hot carrier) and lattice (SHE) temperatures. The next chapter deals with systematic fin-pitch designing approach to mitigate SHE in multi-fin (MF) SOI-FinFET and a Cooperative Game Theory (CGT) framework was employed in this regard. Individual fin contribution to SHE was determined by a combination of T-CAD simulation and CGT model frameworks. Further, a fin pitch optimization rule has been developed, which was found to remain SHE bias and MF-FinFET contact geometry invariant. Since, SHE is nonhomogeneous in MF-FinFET because of variations in heat dissipative paths between fins to the ambience, deriving its analytical model is challenging. From T-CAD modeling of MF-FinFET we have found inter-fin thermal cross talk (TCT) due to non-uniform heat flow between the fins, which finally settles into steady state fin boundary temperatures. The results have been used to write boundary conditions for analytical modeling of SHE in MF-FinFET device, which is the scope of the next contributory chapter. Generalized SHE analytical model encompassing fin, source-drain (S/D) extension and spacer regions had been developed for a MF-FinFET having arbitrary fin numbers, which was later validated using calibrated MF-FinFET T-CAD data. Finally, a multiscale model is presented to predict SHE induced and deformation accelerated oxide breakdown (BD) in a 5 nm SNFET. Calibrated T-CAD setup was utilized to simulate SHE in SNFET while multi-physics simulation was used to determine process induced deformations in nanosheets and adjoining dielectric layers that comprise of hafnium oxide (HfO2) and silicon dioxide (SiO2) interfacial layer (IL). Further, change in defect formation energies (FE) were estimated due to same deformation effect in real space and non-uniform trap generation within dielectric layers wrapping the nanosheets was modelled using a standard thermochemical E model of trap generation with updated FE and SHE as model input. Further, a shortest path search algorithm (A*) was utilized to join the trap generation regions between nanosheets and gate contact depending on their local weights, such that critical BD path could be obtained as useful to assess gate dielectric reliability of SNFET. Concluding remarks and future directions of the thesis work are finally addressed.