DEVELOPMENT OF LATERAL N-TYPE CHARGED PLASMA-BASED HETERO-STRUCTURE JUNCTIONLESS TUNNEL FET

Abstract

Tunnel Field-Effect Transistors (TFETs) have become a popular topic of interest in recent times due to their ability to operate via a tunneling mechanism, which results in lower power dissipation, making them an attractive option for low-power applications. One of the key benefits of TFETs is their ability to exhibit a very low OFF-state current (IOFF) and a steep subthreshold swing (SS ≤ 60 mV/Dec). Additionally, unlike MOSFETs, they are immune to short-channel effects (SCEs) and drain-induced barrier lowering (DIBL). However, while TFETs offer these advantages, they also suffer from limited current driving capability due to the limited amount of charge carriers tunneling through the junction, and ambipolar behavior, which allows conduction for both positive and negative gate voltages. As a result, the use of TFETs in circuit-level applications is hindered. Furthermore, as device feature sizes have decreased below 100 nm, fabrication complexity has become a major concern for this technology node. To address these issues, junctionless TFETs (JLTFETs) have gained significant attention in the semiconductor industry. JLTFETs avoid physical doping to form source, channel, and drain regions, making them immune to random-dopant fluctuations. To further improve the performance of JLTFETs, a new technique called the charge plasma method has been explored for their formation. In this technique, the first entire body is doped with uniform high concentration; it means if we want to make N-type JLTFET, then the entire body is doped with N+ concentration. Then N+-N+-N+ structure is converted into the required P+-I-N+ form using two gates: a polar gate and a control gate on the source and channel, respectively. The work function of the polar gate is kept high to convert the N+ source into the form of the P+ source, and the work function of the control gate is kept lower than the polar gate so that it can convert the N+ channel into the form of an intrinsic channel. By using this method, the barrier that exists between the source and gate electrode in conventional JLTFETs is eliminated, leading to reduced fabrication complexity.