COMPACT MODELLING OF STT-MRAM

Abstract

The volume of data transferred and processed over the internet is expanding every day, necessitating secure data communication/storage and novel computing primitives, thanks to the widespread adoption of mobile computing and the Internet of Things (IoT). Although microelectronics-based computing systems have continuously improved over the last 50 years as a result of aggressive technical scaling, they are presently hampered by high power consumption and intrinsic performance limitations associated with traditional computer architecture. Developing memory technologies are gaining popularity in this environment due to their nonvolatility and low power, fast operation. Experimental characterization & modelling of spin-transfer torque magnetic memory [STT-MRAM] are discussed in this chapter, with a special emphasis on cycling durability and switching variability, which both pose challenges for STT-based memory applications. This thesis presents two new developments in the areas of resistance-voltage model of STT-MRAM and an updated model of write error rate (probability of not switching). The new models are compared with existing works to highlight the benefit. Precise modelling of Magnetic-Tunnel Junction (MTJ) is critical for design of STT MRAM. This thesis reviews R-V model for the MTJ and evaluates them against our proposed model in VerilogA. Existing R-V models are symmetrical in nature whereas our proposed model can account for asymmetry and hence is a better match for experimental data. In the RV modelling of STT-MRAM, resistance and TMR depends on various factors like temperature variations, influence of magnon and bias dependence. These all are modelled. Furthermore, we have discussed the modelling of critical current. We have also developed new model of write error rate (WER) and compared it with the older WER model. We have validated our model with Fokker plank simulations of WER.