VARIATION AWARE TIMING ANALYSIS IN DIGITAL CIRCUITS

Abstract

To reduce the recharacterization effort due to process, Voltage, and On-chip Temperature variations (PVT variations) in ecsm characterization, variation aware timing models are developed that include second order effects such as Velocity Saturation, DIBL, short channel effects and work on long input transition times.Thereafter, with the goal of achieving Variation aware STA (using this work to calculate the delay of a data path and other Timing Analysis), a tool is developed in Python that uses the timing models developed in this work to calculate Delays, TCPs. Due to slight mismatch between simulation and model estimated TCPs for a few TCPs (which occur when node starts its transition), an analysis on overshoot time period is also performed. In the characterised.lib files, With the observation of Impact input transition time on Input capacitance of standard cell and as ecsm_capacitance is also a part of the timing, to characterize capacitance of the standard cell a model to estimate the input capacitance is developed and validated. Mentor Graphics Eldo simulator is used for all the spice simulations, Bash scripting to extract the Data and a python script to generate the .lib file.