SENSING ARCHITECTURES OF MONOLITHIC 3D-DRAM INCLUDING PARASITICS

Abstract

The Monolithic 3D-DRAM is one of the techniques to eliminate the need to decrease the feature size of the DRAM transistor to get the more density to get the cheaper memory per generation by removing the requirement to have advanced lithographic techniques to reduce transistor size. In a way, 3D-DRAM is achieved by two ways: to explore the die in a vertical direction by having multiple layers of stacked memory monolithically, which is the topic of our interest, and other is by advanced 3D assembly technology using "Through silicon vias (TSVs)" for assembling different dies. The monolithic 3D-DRAM has the advantages of cost efficiency and high bandwidth compared to the same generation 2D-DRAM. In this work, we proposed and simulated the entire monolithically stacked 3D-DRAM array in two different configurations of the common bit-line and common word-line. For the purpose of simulation, we took 192-bit as the memory capacity. We divided the whole 192 bits into three memory layers, each with 64 bits, and each layer is further divided into four banks, each with 16 bits, for both common bit-line and common word-line configurations. In each structure, we placed the layers of the DRAM array on top of the bottom most layer, which consists of total control circuitry, which includes peripherals required for all layers to achieve the area and costefficiency. We modelled interconnection between layers as RC and RLC and did simulate by taking parasitic R, C values and R, L, and C values for interconnection between successive layers and by changing type of sense amplifiers in peripheral layer such as voltage sensing, current sensing schemes. For both types of interconnection modelling between successive levels, the delay increases as we move higher layers for both read and write operations in the case of common word-line configuration. In the case of common bit-line configuration, there is no delay between different layers for both read and write operations for both types of interconnection modelling between successive layers. We also compared both 192-bit, three layered of each 64 bits 3D-DRAM common bit-line array and common word-line array.