DESIGN AND COMPACT MODELING OF FERROELECTRIC AND ULTRARAM DEVICES FOR ADVANCED MEMORY TECHNOLOGIES

Abstract

With the ongoing advancement of CPU performance in line with Moore’s law and Dennard scaling, the memory responsible for supporting these highly capable processors is facing challenges in maintaining a similar pace of progress. Storage and memory technology has not improved at the same rate as logic devices. Industry and academic research efforts are focusing on memory technologies, especially with the advent of portable devices with huge functionalities. With the ongoing advancement of CPU performance in line with Moore’s law and Dennard scaling, the memory responsible for supporting these highly capable processors is facing challenges in maintaining a similar pace of progress. This processor-memory performance gap degrades the overall computer system performance. The traditional memory industry is dominated by charge-based memories such as SRAM, DRAM, and flash. However, each of these memory technologies has its own unique drawbacks. To overcome this problem and meet the growing demands of computing systems, there is an immediate need to achieve the contradictory requirement of non-volatility and low-energy operation in future memory systems. The ideal memory device would possess several key characteristics, including fast write/read speeds (< ns), low operating voltage (< 1V), low energy consumption ( f J/bit for write/read), long data retention time (> 10 years), high write/read cycling endurance (> 1017 cycles), and excellent scalability (< 10 nm). Achieving all of these ideal characteristics in a single “universal” memory device is a difficult task. To address this, various emerging Non-Volatile Memory (NVM) technologies have been pursued to fulfil some of these ideal characteristics. These emerging NVM candidates include Phase-change random-access memory (PCRAM), Resistive RAM, Spin- Transfer-Torque (STT)-RAM, Ferroelectric devices, ULTRARAM, etc. Our efforts primarily focused on ULTRARAM and Ferroelectric memories since these devices are cost-effective to fabricate and utilize well-understood techniques. These memories have been experimentally demonstrated, though additional research efforts are required to make them industry standard. On the other hand, the modern semiconductor industry is strongly influenced by Moore’s Law, which has been enabled by the continuous miniaturization of semiconductor devices, allowing the advancement in their functionality at a lower cost. In current technology trends, a variety of multi-gate field-effect transistors (FETs), such as FinFET, gate-all-around (GAA) FETs, forksheets, etc., have been proposed for improved gate controllability and to meet the current technology performance requirements. However, these devices face several scaling issues for sub-3 nm technology nodes. Complementary FET (CFET) with folded pFET/nFET is a promising candidate for Complementary Metal-Oxide-Semiconductor (CMOS) scaling beyond the 3nm technology node, which provides the layout area reduction for the CMOS process. CMOS-compatible ferroelectric-based negative capacitance FET (NCFET) has been reported as an emerging technology that overcomes the fundamental limit of conventional CMOS technology (60mV/dec). It can be used in low-power circuit applications due to internal voltage amplification provided by the ferroelectric layer. Additionally, it can offer higher ON current and low threshold voltage compared to conventional FETs, which can lead to improved switching speed and better electrostatic control. Hence, negative capacitance as a gate stack provides a promising solution for upcoming technology nodes.