Please use this identifier to cite or link to this item: http://localhost:8081/jspui/handle/123456789/20017
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dc.contributor.authorAshai, Aasim-
dc.date.accessioned2026-03-27T10:43:55Z-
dc.date.available2026-03-27T10:43:55Z-
dc.date.issued2025-08-
dc.identifier.urihttp://localhost:8081/jspui/handle/123456789/20017-
dc.guideSarkar, Biplab and Roy, Sourajeeten_US
dc.description.abstractThe continued scaling of CMOS technologies has driven the evolution of transistor architectures from planar MOSFETs to advanced three-dimensional geometries such as FinFETs and Gate-All-Around FETs (GAAFETs). These structures, while offering superior electrostatic control and scalability, significantly increase the complexity of device behavior and, in turn, the challenge of accurate modeling. Modern compact models, such as BSIM-CMG, incorporate numerous interdependent parameters to capture quantum confinement, short-channel effects, and geometry-aware behavior, making their calibration both critical and computationally demanding. In this context, inverse design—inferring physical or compact model parameters from observed or desired electrical responses—has emerged as a crucial but challenging task. Conventional techniques rely on iterative optimization or expert-driven tuning, often struggling with high-dimensional parameter spaces, non-uniqueness of solutions, lack of user control and scalability limitations. This thesis proposes a suite of deep learning-based frameworks to overcome these barriers and enable fast, reliable, and controllable inverse design for nanoscale semiconductor devices. First, a cascaded artificial neural network (ANN) architecture is introduced to enforce consistency between predicted parameters and electrical outputs via integrated forward supervision. Next, a custom-range inverse design approach is presented using floating normalization, allowing user-defined constraints to guide solution space exploration. Finally, a Normalizing Flow-based generative model is employed to detect and reject out-of-distribution targets, improving robustness by filtering physically infeasible targets. Validated on FinFET and GAAFET datasets generated through TCAD simulations, the proposed methods demonstrate significant improvements in accuracy, flexibility, and physical validity. Collectively, this work advances the state of inverse modeling by integrating deep learning with domain-specific physical constraints, offering practical tools for future device modeling and design automation.en_US
dc.language.isoenen_US
dc.publisherIIT Roorkeeen_US
dc.titleDeep Learning Approaches to Inverse Design in Semiconductor Devicesen_US
dc.typeThesisen_US
Appears in Collections:DOCTORAL THESES (E & C)

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