SPIN BASED DEVICES FOR MEMORY AND COMPUTING

Abstract

Over recent decades, advancements in fabrication technology have enabled continuous downsizing of Complementary Metal Oxide Semiconductor (CMOS) technology, in accordance with Moore's Law and resulting in consistent performance improvements of the integrated circuits. However, further downscaling is leading CMOS technology closer to the physical constraints, resulting in high leakage current and performance instability. In addition, higher operating speed and longer global interconnects contribute to a significant rise in dynamic power consumption. At the same time, the explosive growth in artificial intelligence (AI) and data-centric computing applications necessitate a radical departure from traditional von Neumann computing systems due to memory wall associated with limited bandwidth and high energy and latency overheads. In order to address these challenges, spintronics has emerged as one of the promising post-CMOS technologies for data storage and information processing while offering advantages such as ultra-low switching energy, non-volatility, high integration density, and compatibility with CMOS technology. Among the major spintronic storage devices, magnetic tunnel junctions (MTJ), domain wall (DW) nanowires, and skyrmions show significant promise. These devices employ various magnetization switching techniques, including spin-transfer torque (STT), spin-orbit torque (SOT), voltage-controlled magnetic anisotropy (VCMA), strain control, and other hybrid methods, contributing to their potential applications in next-generation memory, logic implementation, and computing. Although, STT-magneto resistive random access memory (MRAM) has been regarded a promising candidate for next-generation scalable and lowpower memory applications, it still has limited endurance, low switching speed (~10-20ns) and large switching current requirements. The use of SOT-MTJ is beneficial in separating the read and write paths to enable high endurance, while achieving low energy and fast switching speed (~5-10ns). The main disadvantage of SOT-MRAM is larger footprint area because of two access transistors, therefore, affecting the storage density of MRAM technology. Multilevel cell (MLC) designs offer a promising solution to improve the storage density of magnetic random access memory. However, in conventional approaches stacking of multiple MTJs increase the complexity and make it challenging to maintain low switching current, high speed, and minimal size of driving transistor. In comparison to STT and SOT mechanisms, voltage and strain controlled memory offered dramatic reduction in power dissipation (a few fJ/bit), switching latency (~1ns). Although significant results have been achieved in voltage-controlled MRAM, the VCMA coefficient at the current stage is relatively small (typically ~60 fJ/Vm) to achieve effective voltage scaling. In addition to above challenges, reliability of the MRAM remains one of the most important issues to be resolved. The complexity of switching operation originates from various factors such as thermal fluctuations, process variations, inhomogeneity in material properties, self-heating, back-hopping, and effect of stray fields, resulting in write errors. The applications of spintronic devices are extensive as they can help integrate new functionalities to establish an efficient computing paradigm at system level. Spintronic devices such as MTJ, DW device and skyrmions have recently been adopted across various computing paradigms including in-memory computing, neuromorphic computing, and stochastic computing. Despite their potential, current designs still encounter challenges in fully harnessing spintronic memories. In neuromorphic computing, these devices face challenges such as limited tunnel magneto-resistance (TMR), implementing controlled analog conductance change, limited scalability, and the adverse effects of device variations. The stochastic nature of spintronic devices also offers opportunities for approximate computing techniques, enabling hardware-efficient, low-power data processing, and hardware security applications. Yet, addressing challenges involves developing mechanisms to exploit this stochastic nature of spintronic devices effectively and optimizing strategies for specific application domains.