MODELING AND OPTIMIZATION OF FINFET/NANOSHEET FET FOR HIGH-FREQUENCY APPLICATIONS

Abstract

In modern technology, the semiconductor industry is seeking new solutions for more energyefficient and high-speed devices. Due to compact sizing and easy handling, users of these electronic devices have increased drastically in the last few decades. In the rapidly evolving consumer electronics industry, designers struggle to create faster designs due to frequent product updates. Accurate mathematical modeling serves as the best solution for enabling rapid and precise optimization of emerging devices. Based on transistor physics, these models efficiently replicate intricate characteristics, facilitating efficient design cycles. This thesis presents a comprehensive exploration of numerical simulation and analytical model-based analyses for optimizing both low-power Silicon 3-D FinFETs and high-power Gallium Nitride vertical junctionless (VJ) power Fin-MOSFET devices. The analytical model, employing the perimeter-weighted sum method, efficiently captures parametric variations in Tri-gate bulk Fin-FETs, offering a fast alternative to TCAD simulations, particularly suitable for light to moderately doped channels. The chapter introduces an enhanced analytical model for high-power devices, addressing the limitations of existing models in considering the distance between the gate and source contact. The model accurately predicts key operational parameters for power devices, such as the maximum source-to-drain potential barrier and its dependence on large drain bias. Moving to low-power 3-D FinFET technology, the study delves into multi-fin FinFET structures, discussing the trade-off between increased ON-current and higher parasitics, especially for highfrequency (HF) applications. The proposed NQS small-signal model for MF-FinFET is introduced, enabling accurate predictions of device parameters beyond 100 GHz. The study divides the frequency range to capture the changing slope of resistance, offering insights into the behavior of Y-parameters above 50 GHz. The impact of geometrical variations on gate resistance and key figures-of-merit (FoMs) is thoroughly investigated, addressing the sensitivity of FoMs in the sub-THz frequency range. The research extends its focus to the reliability of p-FinFETs, specifically addressing the impact of NBTI degradation on single and multi-fin FinFET structures. The study evaluates parameter changes, emphasizing variations in Subthreshold Slope (SS), transconductance (gm), and Drain Induced Barrier Lowering (DIBL) under NBTI stress. The investigation extends to circuit aspects, analyzing the effect on Voltage Transfer Characteristic (VTC) and transient behavior in an inverter and Ring Oscillator (RO). The study provides valuable insights for designing reliable FinFET-based Physical Unclonable Functions (PUFs), exploiting process variations for improved uniqueness and efficient power utilization. Finally, in the context of scaling beyond 5nm node, the research explores stacked Nanosheet FETs (NSFETs) as an alternative to FinFETs, addressing challenges related to gate control and performance improvement. Different configurations of NSFETs are analyzed through TCAD simulations, considering inter-sheet capacitance and proposing design guidelines for optimal RF performance. The study also explores the impact of dual-dielectric spacers in NSFETs, offering valuable insights for future highly scaled transistor designs for low power and high-frequency applications. We also propose a machine learning approach to assist the TCAD results in realizing a local cost and time-effective simulator for analyzing the performance metric of the vertically stacked Nanosheet FET (NSFET). We use Sentaurus TCAD to obtain the results and further realized a local simulator using an XGBoost model to analyze process variations and the role of uneven radii corners in NSFET.