DESIGN OF NEURAL NETWORK AND IMAGE PROCESSING ACCELERATORS USING SPIN BASED DEVICES

Abstract

Artificial intelligence technology that matches the data processing ability of a biological brain to accomplish complicated tasks including image classification, has attracted significant attention. Neuromorphic engineering utilizes very-large-scale integration (VLSI) systems mostly consisting of analog and mixed-signal circuits to replicate functionality of neural architectures of the biological neural system. However, present systems lack the compactness and low-power implementation of the human brain popularly termed as von Neumann bottleneck. The advancement in present CMOS technology faces interruption majorly due to few serious issues. First one is a rise in standby power dissipation and the second is input/output (I/O) bottleneck owing to interconnection delay. These issues can be addressed using nonvolatile (NV) memristive memories. Memristive devices in general, modulate the electrical current flow in a circuit or system and memorize the amount of charge flowing through it and retain the information, even if the power is turned off. Amid the developed NVMs, spin-based magneto-resistive random-access memories (MRAM) have been quite attractive due to high-speed, low-voltage operation, and significant endurance. This work primarily focuses on the investigation of architectures for image processing and neural network accelerator with various multi-level MRAM devices. The framework for complete device to application level for various applications is presented in this work. Firstly, a comparison of various multi-level MRAM devices-based cache memory implementation and binary neural network (BNN) is presented. Then, a voltage-controlled differential MRAM is presented with its application for convolutional neural networks (CNNs) for image recognition with standard datasets and standard network architectures. A device-circuit-architecture framework is presented and utilized for performance evaluation of various non-volatile memory and MRAM based architectures. Further, conventional spin-orbit torque (SOT) MRAM based spiking neuron and synapse is shown for spiking neural networks (SNNs). Then, all spin based SNN is evaluated for various deep neural network architectures. Finally, we leveraged the advantages of spintronic devices for in-memory computing in image edge detection application.