PERFORMANCE ENHANCEMENT OF 3D NAND FLASH MEMORY

Abstract

The NAND flash memory holds about 90% of the non-volatile memory market due to its wide applications which include Solid State Drives (SSDs), Mobile Phones, MP3/MP4 players, digital cameras and USB flash drives. The charge trap-based gate-all-around (GAA) floating gate MOSFET is one of the most prevalent 3D NAND flash memory technology due to its superior channel controllability and CMOS compatibility. In this work we investigate and analyze various novel techniques to optimize 3D NAND flash memory for enhanced performance and reduced variability. Sentaurus TCAD tool is used in this work. We start with the TCAD calibration of our simulation setup with the experimental data. Using TCAD simulations we work on three high-value-problems (HVPs) in the state-of-the-art 3D-NAND flash memory. These HVPs include the performance degradation due to the following sources of variability in the modern 3D-NAND flash memory devices: (i) grain boundary traps, (ii) tapered etch and hence tapered channel profiles, and (iii) pillar-to-pillar variability of the select transistors. The string read current (Iread) reduction with rising pillar height (mold height) and polysilicon channel grain boundary traps is one of the major hurdle in the development of 3D NAND flash memory. We have investigated Iread with variation in polysilicon channel grain size (GS), grain boundary trap density, and channel thickness (TSi). We find that under a critical value of GS, Iread decreases with increase in TSi. This is attributed to the fact that with smaller GS, the total number of grain boundaries and associated traps are significantly higher. Moreover, there exists a typical value of GS for which Iread is independent of TSi, which is desirable to minimize the deviations in Iread arising from TSi variations. The resulting tradeoff in the design of more efficient 3D NAND flash is demonstrated and discussed. Further, it is found that the degradation in Iread can be significantly minimized by limiting the grain boundary trap concentration in polysilicon channel below 1012 cm−2. The results presented are crucial for optimizing Iread and program/erase threshold voltage (VT) window, and serve as the key guidelines in the design of 3-D NAND flash memory with better performance. The channel tapering from top to bottom is another major concern in vertical channel 3D NAND flash memory. This leads to non-uniformity in the threshold voltage (VT) and cell current ii (Icell) distributions along the vertical NAND strings. In this work, we show that the variation in the electric field due to difference in the channel radius from top to bottom is the root cause behind the VT and Icell variations from top to bottom along the string. For the first time, we propose novel techniques to minimize the adverse effects of the channel tapering on VT and Icell variations. It is shown that an optimized channel doping (~1018 cm-3 at the bottom to ~1015 cm-3 at the top), results in narrowing of the VT distribution by ~80% along the string. It is shown that a non-uniform block oxide thickness along the string leads to an enhanced uniformity of VT distribution from bottom to top. Additionally we investigate and show that the uniformity in VT distribution of the different word line (WL) transistors is also achieved by optimizing the amplitude and duration of the program/erase voltages. These results are of significant importance for reliable future 3D NAND flash memories with enhanced uniformity in the program/erase VT window and Icell distributions. The threshold voltage variability of the select transistors is an important issue in the development of 3D NAND flash memory. Particularly, pillar-to-pillar variations in threshold voltage (VT) of the ground select transistor (GST) is critical across the wafer. The VT variation is attributed to the non-uniformity in the plug height of the epitaxially grown silicon layers in different pillars. Therefore, we propose different techniques to achieve performance uniformity in different strings across the wafer in terms of VT distribution of GST. We show that by optimizing the channel doping and gate metal work function (WF) of the GST, the NAND string VT non-uniformity can be eliminated. It is also shown that VT variability can be further minimized by optimizing GST gate length. Further, we present a two-MOSFET-model for the pillar-to-pillar VT variation across the wafer. This study provides the important results for the designing of 3D NAND memories with an enhanced pillar-to-pillar performance uniformity in strings across the wafer. The proposed techniques for 3D NAND flash memory presented in this thesis are very useful to enable scaling and performance improvement. The results presented in this thesis will also serve as valuable guidelines for the design of high performance, variation tolerant and reliable 3D NAND flash memory.